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authorAlyssa Rosenzweig <[email protected]>2020-05-01 17:34:47 -0400
committerAlyssa Rosenzweig <[email protected]>2020-05-04 11:08:15 -0400
commit31a41bb6a62edf77e9c311064c43fffa1c8fcd8f (patch)
tree5b219481779ad3fcac5a86bb94898fabaa170917 /src/panfrost/bifrost
parente14e3065a9f037df5c877057cd53587b58208063 (diff)
pan/bi: Disable CSEL4 emit for now
We need proper scheduling for 4-src ops to work, so for now disable condition fusing so we cap at 3-src at a performance penalty. A bit of a hack but I'd rather not build hacks into a scheduler that will be rewritten soon anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
Diffstat (limited to 'src/panfrost/bifrost')
-rw-r--r--src/panfrost/bifrost/bifrost_compile.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index a14314b6ad3..945d0190762 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -773,8 +773,12 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
alu.src[1] = BIR_INDEX_ZERO;
alu.src_types[1] = alu.src_types[0];
+ /* TODO: Reenable cond fusing when we can split up registers
+ * when scheduling */
+#if 0
bi_fuse_csel_cond(&alu, instr->src[0],
&constants_left, &constant_shift, comps);
+#endif
} else if (alu.type == BI_BITWISE) {
/* Implicit shift argument... at some point we should fold */
alu.src[2] = BIR_INDEX_ZERO;