diff options
author | Alyssa Rosenzweig <[email protected]> | 2020-04-01 09:50:38 -0400 |
---|---|---|
committer | Marge Bot <[email protected]> | 2020-04-05 23:26:04 +0000 |
commit | fbe504e2217a06930cbd62e775435b8234006a02 (patch) | |
tree | ba85cf7d68e62ab23fe7d694acad085ce49c131f /src/panfrost/bifrost/test/bi_interpret.c | |
parent | 7904a29340e151361421384d05bed0bdf4077b14 (diff) |
pan/bit: Handle read/write
We case the various sources and destinations to model register file
access and passthrough in particular.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
Diffstat (limited to 'src/panfrost/bifrost/test/bi_interpret.c')
-rw-r--r-- | src/panfrost/bifrost/test/bi_interpret.c | 54 |
1 files changed, 46 insertions, 8 deletions
diff --git a/src/panfrost/bifrost/test/bi_interpret.c b/src/panfrost/bifrost/test/bi_interpret.c index fb68752c15d..608dfea8f71 100644 --- a/src/panfrost/bifrost/test/bi_interpret.c +++ b/src/panfrost/bifrost/test/bi_interpret.c @@ -39,26 +39,58 @@ typedef union { /* Interprets a subset of Bifrost IR required for automated testing */ static uint64_t -bit_read(struct bit_state *s, bi_instruction *ins, unsigned index, nir_alu_type T) +bit_read(struct bit_state *s, bi_instruction *ins, unsigned index, nir_alu_type T, bool FMA) { - /* STUB */ - return 0; + if (index & BIR_INDEX_REGISTER) { + uint32_t reg = index & ~BIR_INDEX_REGISTER; + assert(reg < 64); + return s->r[reg]; + } else if (index & BIR_INDEX_UNIFORM) { + unreachable("Uniform registers to be implemented"); + } else if (index & BIR_INDEX_CONSTANT) { + return ins->constant.u64 >> (index & ~BIR_INDEX_CONSTANT); + } else if (index & BIR_INDEX_ZERO) { + return 0; + } else if (index & (BIR_INDEX_PASS | BIFROST_SRC_STAGE)) { + return FMA ? 0 : s->T; + } else if (index & (BIR_INDEX_PASS | BIFROST_SRC_PASS_FMA)) { + return s->T0; + } else if (index & (BIR_INDEX_PASS | BIFROST_SRC_PASS_ADD)) { + return s->T1; + } else if (!index) { + /* Placeholder */ + return 0; + } else { + unreachable("Invalid source"); + } } static void -bit_write(struct bit_state *s, unsigned index, nir_alu_type T, bit_t value) +bit_write(struct bit_state *s, unsigned index, nir_alu_type T, bit_t value, bool FMA) { - /* STUB */ + /* Always write stage passthrough */ + if (FMA) + s->T = value.u32; + + if (index & BIR_INDEX_REGISTER) { + uint32_t reg = index & ~BIR_INDEX_REGISTER; + assert(reg < 64); + s->r[reg] = value.u32; + } else if (!index) { + /* Nothing to do */ + } else { + unreachable("Invalid destination"); + } } void -bit_step(struct bit_state *s, bi_instruction *ins) +bit_step(struct bit_state *s, bi_instruction *ins, bool FMA) { /* First, load sources */ bit_t srcs[BIR_SRC_COUNT] = { 0 }; bi_foreach_src(ins, src) - srcs[src].u64 = bit_read(s, ins, ins->src[src], ins->src_types[src]); + srcs[src].u64 = bit_read(s, ins, ins->src[src], ins->src_types[src], FMA); /* Next, do the action of the instruction */ bit_t dest = { 0 }; @@ -96,5 +128,11 @@ bit_step(struct bit_state *s, bi_instruction *ins) } /* Finally, store the result */ - bit_write(s, ins->dest, ins->dest_type, dest); + bit_write(s, ins->dest, ins->dest_type, dest, FMA); + + /* For ADD - change out the passthrough */ + if (!FMA) { + s->T0 = s->T; + s->T1 = dest.u32; + } } |