diff options
| author | Francisco Jerez <[email protected]> | 2016-09-02 17:57:34 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-09-14 14:50:54 -0700 |
| commit | a5bbe4c127c15240758a8cc6144197510c029083 (patch) | |
| tree | cbeee6256fb8f3895f94954d847f351725de1206 /src/mesa | |
| parent | 717d8efd584d8db7fbbdbe7deb51371e28d6c492 (diff) | |
i965/vec4: Take into account misalignment in regs_written() and regs_read().
Unlike the FS counterpart of this commit this was likely not (yet) a
bug, but let's fix it already in preparation for implementing support
for sub-GRF offsets in the VEC4 back-end.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_ir_vec4.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index 2fd5441167a..9910d87d61e 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h @@ -263,9 +263,10 @@ set_saturate(bool saturate, vec4_instruction *inst) inline unsigned regs_written(const vec4_instruction *inst) { - /* XXX - Take into account register-misaligned offsets correctly. */ + /* XXX - Use reg_offset() as promised by the comment above. */ assert(inst->dst.file != UNIFORM && inst->dst.file != IMM); - return DIV_ROUND_UP(inst->size_written, REG_SIZE); + return DIV_ROUND_UP(inst->dst.offset % REG_SIZE + inst->size_written, + REG_SIZE); } /** @@ -277,10 +278,11 @@ regs_written(const vec4_instruction *inst) inline unsigned regs_read(const vec4_instruction *inst, unsigned i) { - /* XXX - Take into account register-misaligned offsets correctly. */ + /* XXX - Use reg_offset() as promised by the comment above. */ const unsigned reg_size = inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 16 : REG_SIZE; - return DIV_ROUND_UP(inst->size_read(i), reg_size); + return DIV_ROUND_UP(inst->src[i].offset % reg_size + inst->size_read(i), + reg_size); } } /* namespace brw */ |