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authorChris Forbes <[email protected]>2012-11-22 16:23:23 +1300
committerKenneth Graunke <[email protected]>2012-11-26 14:02:30 -0800
commit894fe54ec9b859b9fa47cc153fdc3c23cb98455e (patch)
treec8b840d1e01ff7ac515618333c6aaacd1dbf95de /src/mesa
parent8f3570efc740dc36305c99b8c932a02427975cc9 (diff)
i965/vs: add support for emitting SHL, SHR, ASR
Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp11
2 files changed, 10 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 5f35de59bb5..ac1fb46875b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -353,6 +353,9 @@ public:
vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
uint32_t condition);
vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 72766a2c29d..be5f8f2f99c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -120,6 +120,9 @@ ALU2(XOR)
ALU2(DP3)
ALU2(DP4)
ALU2(DPH)
+ALU2(SHL)
+ALU2(SHR)
+ALU2(ASR)
/** Gen4 predicated IF. */
vec4_instruction *
@@ -1324,14 +1327,14 @@ vec4_visitor::visit(ir_expression *ir)
break;
case ir_binop_lshift:
- inst = emit(BRW_OPCODE_SHL, result_dst, op[0], op[1]);
+ inst = emit(SHL(result_dst, op[0], op[1]));
break;
case ir_binop_rshift:
if (ir->type->base_type == GLSL_TYPE_INT)
- inst = emit(BRW_OPCODE_ASR, result_dst, op[0], op[1]);
+ inst = emit(ASR(result_dst, op[0], op[1]));
else
- inst = emit(BRW_OPCODE_SHR, result_dst, op[0], op[1]);
+ inst = emit(SHR(result_dst, op[0], op[1]));
break;
case ir_binop_ubo_load: {
@@ -1350,7 +1353,7 @@ vec4_visitor::visit(ir_expression *ir)
if (const_offset_ir) {
offset = src_reg(const_offset / 16);
} else {
- emit(BRW_OPCODE_SHR, dst_reg(offset), offset, src_reg(4));
+ emit(SHR(dst_reg(offset), offset, src_reg(4)));
}
vec4_instruction *pull =