diff options
| author | Kenneth Graunke <[email protected]> | 2014-04-16 20:15:23 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-04-17 10:54:00 -0700 |
| commit | 71846a943f9b699d0f234d919dcb8d1934943693 (patch) | |
| tree | f8a2eba2b1bca770ebf4df0116c9d7f648c28689 /src/mesa | |
| parent | ee10e893cbd616da295dc46ca37ece664cd91d1a (diff) | |
i965: Retype pre-Gen6 varying pull load destination to UW.
This sets up the proper execution mask for sends in SIMD16 mode.
Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2,
glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake,
which regressed when I enabled SIMD16 pull parameter support in
commit b207e88b25e526d0f1ada7b19605b880a27866dc.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index c6b4aae4087..ff85171bb61 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -912,7 +912,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst, struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); send->header.compression_control = BRW_COMPRESSION_NONE; - brw_set_dest(p, send, dst); + brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW)); brw_set_src0(p, send, header); if (brw->gen < 6) send->header.destreg__conditionalmod = inst->base_mrf; |