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authorTimothy Arceri <[email protected]>2017-04-08 10:29:22 +1000
committerTimothy Arceri <[email protected]>2017-04-10 10:55:34 +1000
commit6c02387b2c882b69de542de81f3ed121665ae198 (patch)
tree326833e69de919d1bd47c09a424f42ab9210575d /src/mesa
parent1b85009ec14ded1b51e3ceafc748b8f5ee732874 (diff)
radeon: take ownership rather than adding reference for new renderbuffers
This avoids locking in the reference calls and fixes a leak after the RefCount initialisation was change from 0 to 1. Fixes: 32141e53d1520 (mesa: tidy up renderbuffer RefCount initialisation) Reviewed-by: Emil Velikov <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 06901348a39..fab2eeab6c9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -677,13 +677,13 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
/* front color renderbuffer */
rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
+ _mesa_add_renderbuffer_without_ref(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
rfb->color_rb[0]->has_surface = 1;
/* back color renderbuffer */
if (mesaVis->doubleBufferMode) {
rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
+ _mesa_add_renderbuffer_without_ref(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
rfb->color_rb[1]->has_surface = 1;
}
@@ -691,21 +691,21 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
if (mesaVis->stencilBits == 8) {
struct radeon_renderbuffer *depthStencilRb =
radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
+ _mesa_add_renderbuffer_without_ref(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base);
depthStencilRb->has_surface = screen->depthHasSurface;
} else {
/* depth renderbuffer */
struct radeon_renderbuffer *depth =
radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
+ _mesa_add_renderbuffer_without_ref(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
depth->has_surface = screen->depthHasSurface;
}
} else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct radeon_renderbuffer *depth =
radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
+ _mesa_add_renderbuffer_without_ref(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
depth->has_surface = screen->depthHasSurface;
}