diff options
| author | Kenneth Graunke <[email protected]> | 2013-07-10 13:39:19 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-07-15 19:40:52 -0700 |
| commit | 3b3a440d2be8ffc7354293e79133f7045487dd8a (patch) | |
| tree | 6f92d262dbabe0494bf4ee220306c27c48db65ea /src/mesa | |
| parent | 9a86875c6b3245769367f3f42d9452e6de15b0bd (diff) | |
i965: Cite the Ivybridge PRM for VS PIPE_CONTROL workarounds.
Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index ab7a9a37031..7f4121cb943 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -419,8 +419,8 @@ intel_emit_depth_stall_flushes(struct brw_context *brw) } /** - * From the BSpec, volume 2a.03: VS Stage Input / State: - * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth + * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input): + * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS, * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS, * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs |