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authorCaio Marcelo de Oliveira Filho <[email protected]>2018-06-29 11:38:09 -0700
committerRafael Antognolli <[email protected]>2018-07-12 14:03:51 -0700
commit094225d69d25239a36daebb0021235cce65afa59 (patch)
tree618f76d7ab3baf937b54f10952a771660560c103 /src/mesa
parentfa0c19d17b9b6308fdca01f609c167b3ea1e68ae (diff)
i965: fix typo (wrong gen number) in comment
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/genX_state_upload.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 7fe12887030..4a68bbe3d13 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1935,7 +1935,7 @@ genX(upload_wm)(struct brw_context *brw)
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2));
}
#elif GEN_GEN == 6
- /* On gen5, we have multiple shader kernels and we no longer specify a
+ /* On gen6, we have multiple shader kernels and we no longer specify a
* register count for each one.
*/
wm.KernelStartPointer0 = stage_state->prog_offset +