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authorIago Toral Quiroga <[email protected]>2018-01-09 09:29:17 +0100
committerIago Toral Quiroga <[email protected]>2018-01-10 08:21:02 +0100
commitdae856eced1d4de966b0e1cfc5f2ed201240571c (patch)
tree97e2a4459c09c7ad47183318bbdb84f710c15dfd /src/mesa
parent4317c848b9c8f5a650815e20c792fc9f3564b68e (diff)
i965: lower gl_PatchVerticesIn to a uniform
We want this here instead of nir_lower_system_values because for Vulkan we don't want this lowering to take place. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: do this also for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 5b168c25e3d..f6c7e4515c4 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -88,6 +88,14 @@ brw_create_nir(struct brw_context *brw,
}
nir_validate_shader(nir);
+ /* Lower PatchVerticesIn from system value to uniform. This needs to
+ * happen before brw_preprocess_nir, since that will lower system values.
+ */
+ if ((stage == MESA_SHADER_TESS_CTRL && brw->screen->devinfo.gen >= 8) ||
+ stage == MESA_SHADER_TESS_EVAL) {
+ brw_nir_lower_patch_vertices_in_to_uniform(nir);
+ }
+
nir = brw_preprocess_nir(brw->screen->compiler, nir);
if (stage == MESA_SHADER_FRAGMENT) {