From dae856eced1d4de966b0e1cfc5f2ed201240571c Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Tue, 9 Jan 2018 09:29:17 +0100 Subject: i965: lower gl_PatchVerticesIn to a uniform We want this here instead of nir_lower_system_values because for Vulkan we don't want this lowering to take place. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: do this also for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_program.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 5b168c25e3d..f6c7e4515c4 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -88,6 +88,14 @@ brw_create_nir(struct brw_context *brw, } nir_validate_shader(nir); + /* Lower PatchVerticesIn from system value to uniform. This needs to + * happen before brw_preprocess_nir, since that will lower system values. + */ + if ((stage == MESA_SHADER_TESS_CTRL && brw->screen->devinfo.gen >= 8) || + stage == MESA_SHADER_TESS_EVAL) { + brw_nir_lower_patch_vertices_in_to_uniform(nir); + } + nir = brw_preprocess_nir(brw->screen->compiler, nir); if (stage == MESA_SHADER_FRAGMENT) { -- cgit v1.2.3