diff options
| author | Francisco Jerez <[email protected]> | 2016-05-17 16:43:05 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-05-27 23:19:22 -0700 |
| commit | 12ae87abb194e2fc5339d8944b6d0e9ddf54ea22 (patch) | |
| tree | 53205812858a6485614584d0fd0c7d0a3db02cb7 /src/mesa | |
| parent | dea9c1df89cf58591cce83b67d3d905a28f0c101 (diff) | |
i965/fs: Apply usual FPU-like execution size restrictions to MULH.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 22c4d345f5a..000658104af 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -4829,7 +4829,8 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, /* MULH is lowered to the MUL/MACH sequence using the accumulator, which * is 8-wide on Gen7+. */ - return (devinfo->gen >= 7 ? 8 : inst->exec_size); + return (devinfo->gen >= 7 ? 8 : + get_fpu_lowered_simd_width(devinfo, inst)); case FS_OPCODE_FB_WRITE_LOGICAL: /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them |