From 12ae87abb194e2fc5339d8944b6d0e9ddf54ea22 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 17 May 2016 16:43:05 -0700 Subject: i965/fs: Apply usual FPU-like execution size restrictions to MULH. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 22c4d345f5a..000658104af 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -4829,7 +4829,8 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, /* MULH is lowered to the MUL/MACH sequence using the accumulator, which * is 8-wide on Gen7+. */ - return (devinfo->gen >= 7 ? 8 : inst->exec_size); + return (devinfo->gen >= 7 ? 8 : + get_fpu_lowered_simd_width(devinfo, inst)); case FS_OPCODE_FB_WRITE_LOGICAL: /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them -- cgit v1.2.3