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author | Francisco Jerez <[email protected]> | 2016-09-07 14:36:32 -0700 |
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committer | Francisco Jerez <[email protected]> | 2016-09-14 14:50:54 -0700 |
commit | 717d8efd584d8db7fbbdbe7deb51371e28d6c492 (patch) | |
tree | cb86364809aa1e1f09202ac7ab313b0daac5ef46 /src/mesa/x86-64 | |
parent | e540045df5cf5ae17ce640d6d73138444a4ac0d3 (diff) |
i965/fs: Take into account misalignment in regs_written() and regs_read().
There was a workaround for this in fs_inst::size_read() for the
SHADER_OPCODE_MOV_INDIRECT instruction and FIXED_GRF register file
*only*. We should take this possibility into account for the sources
and destinations of all instructions on all optimization passes that
need to quantize dataflow in 32B increments by adding the amount of
misalignment to the size read or written from the regs_read() and
regs_written() helpers respectively.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/mesa/x86-64')
0 files changed, 0 insertions, 0 deletions