diff options
| author | Kenneth Graunke <[email protected]> | 2013-08-13 15:03:12 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-08-15 15:18:48 -0700 |
| commit | c189840b21e176d87cbb382e64e848061b8c7b06 (patch) | |
| tree | 6aa46b9c6f61927e67c3195c886a0ffabb1d8c7a /src/mesa/drivers | |
| parent | 41eef83cc030e7087b79b0070d00fbc56538fb81 (diff) | |
i965: Force X-tiling for 128 bpp formats on Sandybridge.
128 bpp formats are not allowed to be Y-tiled on any architectures
except Gen7.
+11 Piglits on Sandybridge (mostly regression fixes since the
switch to Y-tiling).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63867
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64261
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Cc: "9.2" <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index d6643ca4d72..86a2d53f29f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -468,6 +468,15 @@ intel_miptree_choose_tiling(struct brw_context *brw, if (brw->gen < 6) return I915_TILING_X; + /* From the Sandybridge PRM, Volume 1, Part 2, page 32: + * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX + * or Linear." + * 128 bits per pixel translates to 16 bytes per pixel. This is necessary + * all the way back to 965, but is explicitly permitted on Gen7. + */ + if (brw->gen != 7 && mt->cpp >= 16) + return I915_TILING_X; + return I915_TILING_Y | I915_TILING_X; } |