i965/blorp: Use blorp_address in brw_blorp_surface instead of bo+offset

Signed-off-by: Jason Ekstrand <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>

6 files changed, 64 insertions, 68 deletions

diff --git a/src/mesa/drivers/dri/i965/blorp.c b/src/mesa/drivers/dri/i965/blorp.c
index f2338c9001b..be5adce3295 100644
--- a/src/mesa/drivers/dri/i965/blorp.c
+++ b/src/mesa/drivers/dri/i965/blorp.c
@@ -82,14 +82,12 @@ brw_blorp_surface_info_init(struct brw_context *brw,
    }
 
    info->surf = *surf->surf;
-   info->bo = surf->bo;
-   info->offset = surf->offset;
+   info->addr = surf->addr;
 
    info->aux_usage = surf->aux_usage;
    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
       info->aux_surf = *surf->aux_surf;
-      info->aux_bo = surf->aux_bo;
-      info->aux_offset = surf->aux_offset;
+      info->aux_addr = surf->aux_addr;
    }
 
    info->clear_color = surf->clear_color;
diff --git a/src/mesa/drivers/dri/i965/blorp.h b/src/mesa/drivers/dri/i965/blorp.h
index f3e91f55ce6..a11c24d839d 100644
--- a/src/mesa/drivers/dri/i965/blorp.h
+++ b/src/mesa/drivers/dri/i965/blorp.h
@@ -62,15 +62,20 @@ void blorp_init(struct blorp_context *blorp, void *driver_ctx,
                 struct isl_device *isl_dev);
 void blorp_finish(struct blorp_context *blorp);
 
+struct blorp_address {
+   drm_intel_bo *buffer;
+   uint32_t read_domains;
+   uint32_t write_domain;
+   uint32_t offset;
+};
+
 struct brw_blorp_surf
 {
    const struct isl_surf *surf;
-   drm_intel_bo *bo;
-   uint32_t offset;
+   struct blorp_address addr;
 
    const struct isl_surf *aux_surf;
-   drm_intel_bo *aux_bo;
-   uint32_t aux_offset;
+   struct blorp_address aux_addr;
    enum isl_aux_usage aux_usage;
 
    union isl_color_value clear_color;
diff --git a/src/mesa/drivers/dri/i965/blorp_blit.c b/src/mesa/drivers/dri/i965/blorp_blit.c
index 0291e01da8e..8f41e4f19cc 100644
--- a/src/mesa/drivers/dri/i965/blorp_blit.c
+++ b/src/mesa/drivers/dri/i965/blorp_blit.c
@@ -1297,7 +1297,7 @@ surf_convert_to_single_slice(struct brw_context *brw,
                                       x_offset_sa, y_offset_sa,
                                       &byte_offset,
                                       &info->tile_x_sa, &info->tile_y_sa);
-   info->offset += byte_offset;
+   info->addr.offset += byte_offset;
 
    /* TODO: Once this file gets converted to C, we shouls just use designated
     * initializers.
diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h b/src/mesa/drivers/dri/i965/blorp_priv.h
index 86db7054c86..9857db85793 100644
--- a/src/mesa/drivers/dri/i965/blorp_priv.h
+++ b/src/mesa/drivers/dri/i965/blorp_priv.h
@@ -45,12 +45,10 @@ enum {
 struct brw_blorp_surface_info
 {
    struct isl_surf surf;
-   drm_intel_bo *bo;
-   uint32_t offset;
+   struct blorp_address addr;
 
    struct isl_surf aux_surf;
-   drm_intel_bo *aux_bo;
-   uint32_t aux_offset;
+   struct blorp_address aux_addr;
    enum isl_aux_usage aux_usage;
 
    union isl_color_value clear_color;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index dca8533f821..97ca0e3ce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -136,8 +136,13 @@ brw_blorp_surf_for_miptree(struct brw_context *brw,
 {
    intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
    surf->surf = &tmp_surfs[0];
-   surf->bo = mt->bo;
-   surf->offset = mt->offset;
+   surf->addr = (struct blorp_address) {
+      .buffer = mt->bo,
+      .offset = mt->offset,
+      .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
+                                         I915_GEM_DOMAIN_SAMPLER,
+      .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+   };
 
    if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
        mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
@@ -153,7 +158,7 @@ brw_blorp_surf_for_miptree(struct brw_context *brw,
        */
       uint32_t offset;
       apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
-      surf->offset += offset;
+      surf->addr.offset += offset;
       *level = 0;
    }
 
@@ -172,14 +177,20 @@ brw_blorp_surf_for_miptree(struct brw_context *brw,
       surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
 
       surf->aux_surf = aux_surf;
+      surf->aux_addr = (struct blorp_address) {
+         .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
+                                            I915_GEM_DOMAIN_SAMPLER,
+         .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+      };
+
       if (mt->mcs_mt) {
-         surf->aux_bo = mt->mcs_mt->bo;
-         surf->aux_offset = mt->mcs_mt->offset;
+         surf->aux_addr.buffer = mt->mcs_mt->bo;
+         surf->aux_addr.offset = mt->mcs_mt->offset;
       } else {
          assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
          struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
          if (hiz_mt) {
-            surf->aux_bo = hiz_mt->bo;
+            surf->aux_addr.buffer = hiz_mt->bo;
             if (brw->gen == 6 &&
                 hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
                /* gen6 requires the HiZ buffer to be manually offset to the
@@ -187,22 +198,24 @@ brw_blorp_surf_for_miptree(struct brw_context *brw,
                 * matter since most of those fields don't matter.
                 */
                apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
-                                             &surf->aux_offset);
+                                             &surf->aux_addr.offset);
             } else {
-               surf->aux_offset = 0;
+               surf->aux_addr.offset = 0;
             }
             assert(hiz_mt->pitch == aux_surf->row_pitch);
          } else {
-            surf->aux_bo = mt->hiz_buf->bo;
-            surf->aux_offset = 0;
+            surf->aux_addr.buffer = mt->hiz_buf->bo;
+            surf->aux_addr.offset = 0;
          }
       }
    } else {
-      surf->aux_bo = NULL;
-      surf->aux_offset = 0;
+      surf->aux_addr = (struct blorp_address) {
+         .buffer = NULL,
+      };
       memset(&surf->clear_color, 0, sizeof(surf->clear_color));
    }
-   assert((surf->aux_usage == ISL_AUX_USAGE_NONE) == (surf->aux_bo == NULL));
+   assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
+          (surf->aux_addr.buffer == NULL));
 }
 
 static enum isl_format
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index eb4c4fac376..9f304a3aa42 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -43,13 +43,6 @@ blorp_emit_dwords(struct brw_context *brw, unsigned n)
    return map;
 }
 
-struct blorp_address {
-   drm_intel_bo *buffer;
-   uint32_t read_domains;
-   uint32_t write_domain;
-   uint32_t offset;
-};
-
 static uint64_t
 blorp_emit_reloc(struct brw_context *brw, void *location,
                  struct blorp_address address, uint32_t delta)
@@ -547,7 +540,7 @@ blorp_emit_ps_config(struct brw_context *brw,
    blorp_emit(brw, GENX(3DSTATE_WM), wm);
 
    blorp_emit(brw, GENX(3DSTATE_PS), ps) {
-      if (params->src.bo) {
+      if (params->src.addr.buffer) {
          ps.SamplerCount = 1; /* Up to 4 samplers */
          ps.BindingTableEntryCount = 2;
       } else {
@@ -599,7 +592,7 @@ blorp_emit_ps_config(struct brw_context *brw,
    blorp_emit(brw, GENX(3DSTATE_PS_EXTRA), psx) {
       psx.PixelShaderValid = true;
 
-      if (params->src.bo)
+      if (params->src.addr.buffer)
          psx.PixelShaderKillsPixel = true;
 
       psx.AttributeEnable = prog_data->num_varying_inputs > 0;
@@ -630,7 +623,7 @@ blorp_emit_ps_config(struct brw_context *brw,
       if (prog_data)
          wm.ThreadDispatchEnable = true;
 
-      if (params->src.bo)
+      if (params->src.addr.buffer)
          wm.PixelShaderKillPixel = true;
 
       if (params->dst.surf.samples > 1) {
@@ -672,7 +665,7 @@ blorp_emit_ps_config(struct brw_context *brw,
          ps._16PixelDispatchEnable = true;
       }
 
-      if (params->src.bo)
+      if (params->src.addr.buffer)
          ps.SamplerCount = 1; /* Up to 4 samplers */
 
       switch (params->fast_clear_op) {
@@ -724,7 +717,7 @@ blorp_emit_ps_config(struct brw_context *brw,
          wm.NumberofSFOutputAttributes = prog_data->num_varying_inputs;
       }
 
-      if (params->src.bo) {
+      if (params->src.addr.buffer) {
          wm.SamplerCount = 1; /* Up to 4 samplers */
          wm.PixelShaderKillPixel = true; /* TODO: temporarily smash on */
       }
@@ -794,23 +787,13 @@ blorp_emit_depth_stencil_config(struct brw_context *brw,
       db.MinimumArrayElement = params->depth.view.base_array_layer;
 
       db.SurfacePitch = params->depth.surf.row_pitch - 1;
-      db.SurfaceBaseAddress = (struct blorp_address) {
-         .buffer = params->depth.bo,
-         .read_domains = I915_GEM_DOMAIN_RENDER,
-         .write_domain = I915_GEM_DOMAIN_RENDER,
-         .offset = params->depth.offset,
-      };
+      db.SurfaceBaseAddress = params->depth.addr;
       db.DepthBufferMOCS = mocs;
    }
 
    blorp_emit(brw, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
       hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
-      hiz.SurfaceBaseAddress = (struct blorp_address) {
-         .buffer = params->depth.aux_bo,
-         .read_domains = I915_GEM_DOMAIN_RENDER,
-         .write_domain = I915_GEM_DOMAIN_RENDER,
-         .offset = params->depth.aux_offset,
-      };
+      hiz.SurfaceBaseAddress = params->depth.aux_addr;
       hiz.HierarchicalDepthBufferMOCS = mocs;
    }
 
@@ -944,7 +927,6 @@ static const struct surface_state_info surface_state_infos[] = {
 static uint32_t
 blorp_emit_surface_state(struct brw_context *brw,
                          const struct brw_blorp_surface_info *surface,
-                         uint32_t read_domains, uint32_t write_domain,
                          bool is_render_target)
 {
    const struct surface_state_info ss_info = surface_state_infos[brw->gen];
@@ -969,12 +951,13 @@ blorp_emit_surface_state(struct brw_context *brw,
 
    const uint32_t mocs =
       is_render_target ? brw->blorp.mocs.rb : brw->blorp.mocs.tex;
-   uint64_t aux_bo_offset = surface->aux_bo ? surface->aux_bo->offset64 : 0;
+   uint64_t aux_bo_offset =
+      surface->aux_addr.buffer ? surface->aux_addr.buffer->offset64 : 0;
 
    isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &surface->view,
-                       .address = surface->bo->offset64 + surface->offset,
+                       .address = surface->addr.buffer->offset64 + surface->addr.offset,
                        .aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
-                       .aux_address = aux_bo_offset + surface->aux_offset,
+                       .aux_address = aux_bo_offset + surface->aux_addr.offset,
                        .mocs = mocs, .clear_color = surface->clear_color,
                        .x_offset_sa = surface->tile_x_sa,
                        .y_offset_sa = surface->tile_y_sa);
@@ -982,21 +965,23 @@ blorp_emit_surface_state(struct brw_context *brw,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            surf_offset + ss_info.reloc_dw * 4,
-                           surface->bo,
-                           dw[ss_info.reloc_dw] - surface->bo->offset64,
-                           read_domains, write_domain);
+                           surface->addr.buffer,
+                           dw[ss_info.reloc_dw] - surface->addr.buffer->offset64,
+                           surface->addr.read_domains,
+                           surface->addr.write_domain);
 
    if (aux_usage != ISL_AUX_USAGE_NONE) {
       /* On gen7 and prior, the bottom 12 bits of the MCS base address are
        * used to store other information.  This should be ok, however, because
        * surface buffer addresses are always 4K page alinged.
        */
-      assert((surface->aux_offset & 0xfff) == 0);
+      assert((surface->aux_addr.offset & 0xfff) == 0);
       drm_intel_bo_emit_reloc(brw->batch.bo,
                               surf_offset + ss_info.aux_reloc_dw * 4,
-                              surface->aux_bo,
+                              surface->aux_addr.buffer,
                               dw[ss_info.aux_reloc_dw] & 0xfff,
-                              read_domains, write_domain);
+                              surface->aux_addr.read_domains,
+                              surface->aux_addr.write_domain);
    }
 
    return surf_offset;
@@ -1013,13 +998,10 @@ blorp_emit_surface_states(struct brw_context *brw,
                       32, /* alignment */ &bind_offset);
 
    bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
-      blorp_emit_surface_state(brw, &params->dst,
-                               I915_GEM_DOMAIN_RENDER,
-                               I915_GEM_DOMAIN_RENDER, true);
-   if (params->src.bo) {
+      blorp_emit_surface_state(brw, &params->dst, true);
+   if (params->src.addr.buffer) {
       bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] =
-         blorp_emit_surface_state(brw, &params->src,
-                                  I915_GEM_DOMAIN_SAMPLER, 0, false);
+         blorp_emit_surface_state(brw, &params->src, false);
    }
 
 #if GEN_GEN >= 7
@@ -1188,7 +1170,7 @@ genX(blorp_exec)(struct brw_context *brw,
    if (params->wm_prog_data)
       blorp_emit_surface_states(brw, params);
 
-   if (params->src.bo)
+   if (params->src.addr.buffer)
       blorp_emit_sampler_state(brw, params);
 
    blorp_emit_3dstate_multisample(brw, params->dst.surf.samples);
@@ -1225,7 +1207,7 @@ genX(blorp_exec)(struct brw_context *brw,
 
    blorp_emit_viewport_state(brw, params);
 
-   if (params->depth.bo) {
+   if (params->depth.addr.buffer) {
       blorp_emit_depth_stencil_config(brw, params);
    } else {
       brw_emit_depth_stall_flushes(brw);