diff options
| author | Kenneth Graunke <[email protected]> | 2014-03-20 14:41:43 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-03-21 15:31:45 -0700 |
| commit | 9834058a91031f0b66007357791bb5c4013acc91 (patch) | |
| tree | 2c7680cc152c3adfd031f6f0d5f5438a7e61ee0b /src/mesa/drivers | |
| parent | 351e13c5ad81757a15ab319f2ef521b3921a345c (diff) | |
i965: Drop BLT TexSubImage Y-tiling restriction on Gen6+.
Currently, we don't use this path on Sandybridge because we suspect
other paths will be faster. But we potentially could. If we do, we
should allow it to support Y-tiled BLTs.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_subimage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 6942039fdc9..b65a7720af5 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -98,8 +98,8 @@ intel_blit_texsubimage(struct gl_context * ctx, if (!intelImage->mt) return false; - /* The blitter can't handle Y tiling */ - if (intelImage->mt->region->tiling == I915_TILING_Y) + /* Prior to Sandybridge, the blitter can't handle Y tiling */ + if (brw->gen < 6 && intelImage->mt->region->tiling == I915_TILING_Y) return false; if (texImage->TexObject->Target != GL_TEXTURE_2D) |