Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesa into r600_state_predict

Conflicts:
	src/mesa/drivers/dri/r300/r300_cmdbuf.c
	src/mesa/drivers/dri/radeon/radeon_cmdbuf.h

24 files changed, 632 insertions, 345 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index b3cf524c63e..5f29ca1cd49 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -588,17 +588,19 @@ static void emit_dph( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
+   const int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1;
+
    if (!(mask & WRITEMASK_XYZW))
       return; /* Do not emit dead code */
 
-   assert((mask & WRITEMASK_XYZW) == WRITEMASK_X);
+   assert(is_power_of_two(mask & WRITEMASK_XYZW));
 
    brw_MUL(p, brw_null_reg(), arg0[0], arg1[0]);
    brw_MAC(p, brw_null_reg(), arg0[1], arg1[1]);
-   brw_MAC(p, dst[0], arg0[2], arg1[2]);
+   brw_MAC(p, dst[dst_chan], arg0[2], arg1[2]);
 
    brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-   brw_ADD(p, dst[0], dst[0], arg1[3]);
+   brw_ADD(p, dst[dst_chan], dst[dst_chan], arg1[3]);
    brw_set_saturate(p, 0);
 }
 
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index b08af116a12..87651716fef 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -105,7 +105,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
 	ndw -= 5;
 	OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
 	OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
-	OUT_BATCH_TABLE(atom->cmd + 1, ndw);
+	OUT_BATCH_TABLE(&atom->cmd[1], ndw);
 	OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 	END_BATCH();
 }
@@ -134,7 +134,7 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 	OUT_BATCH(addr);
 	ndw-=3;
 	OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
-	OUT_BATCH_TABLE(atom->cmd + 1, ndw);
+	OUT_BATCH_TABLE(&atom->cmd[1], ndw);
 	END_BATCH();
 }
 
diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c
index 6652b396b9b..2ac898bd59d 100644
--- a/src/mesa/drivers/dri/r300/r300_draw.c
+++ b/src/mesa/drivers/dri/r300/r300_draw.c
@@ -109,11 +109,11 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer
 
 #if MESA_BIG_ENDIAN
 	} else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
-		GLuint size;
 		GLushort *in = (GLushort *)src_ptr;
-		size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
+		GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
 
-		radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offet, size, 4);
+		radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo,
+				     &r300->ind_buf.bo_offset, size, 4);
 
 		assert(r300->ind_buf.bo->ptr != NULL);
 		out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index f3674f9c7b8..446cf40131e 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -390,7 +390,7 @@ void r300RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
 		GLuint first, incr, offset = 0;
 
 		if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) &&
-			num_verts > 65500) {
+			num_verts > 65535) {
 			WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim);
 			return;
 		}
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 38814b6d71e..10ea7668963 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -322,7 +322,7 @@ static int r600_cs_emit(struct radeon_cs *cs)
     struct drm_radeon_cs_chunk cs_chunk[2];
     uint32_t length_dw_reloc_chunk;
     uint64_t chunk_ptrs[2];
-    uint32_t reloc_chunk[128]; 
+    uint32_t reloc_chunk[256];
     int r;
     int retry = 0;
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 4489064c0d0..0b0c4f5049b 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -185,7 +185,13 @@ static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
 
 static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 {
-	/* to be enabled */
+	context_t *context = (context_t *)radeon;
+
+	/* always emit CB base to prevent
+	 * lock ups on some chips.
+	 */
+	R600_STATECHANGE(context, cb_target);
+	r700Start3D(context);
 }
 
 static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index a9b080baa31..8ae05a301c7 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -55,10 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 struct r600_context;
 typedef struct r600_context context_t;
 
-extern GLboolean r700SendPSState(context_t *context);
-extern GLboolean r700SendVSState(context_t *context);
-extern GLboolean r700SendFSState(context_t *context);
-
 #include "main/mm.h"
 
 /************ DMA BUFFERS **************/
@@ -115,17 +111,37 @@ enum
 struct r600_hw_state {
 	struct radeon_state_atom sq;
 	struct radeon_state_atom db;
+	struct radeon_state_atom stencil;
 	struct radeon_state_atom db_target;
 	struct radeon_state_atom sc;
+	struct radeon_state_atom scissor;
+	struct radeon_state_atom aa;
 	struct radeon_state_atom cl;
+	struct radeon_state_atom gb;
 	struct radeon_state_atom ucp;
 	struct radeon_state_atom su;
+	struct radeon_state_atom poly;
 	struct radeon_state_atom cb;
+	struct radeon_state_atom clrcmp;
+	struct radeon_state_atom blnd;
+	struct radeon_state_atom blnd_clr;
 	struct radeon_state_atom cb_target;
 	struct radeon_state_atom sx;
 	struct radeon_state_atom vgt;
 	struct radeon_state_atom spi;
 	struct radeon_state_atom vpt;
+
+	struct radeon_state_atom fs;
+	struct radeon_state_atom vs;
+	struct radeon_state_atom ps;
+
+	struct radeon_state_atom vs_consts;
+	struct radeon_state_atom ps_consts;
+
+	struct radeon_state_atom vtx;
+	struct radeon_state_atom tx;
+	struct radeon_state_atom tx_smplr;
+	struct radeon_state_atom tx_brdr_clr;
 };
 
 /**
@@ -168,22 +184,14 @@ do {							\
 	r600->radeon.hw.is_dirty = GL_TRUE;			\
 } while(0)
 
-extern GLboolean r700SendTextureState(context_t *context);
-
 extern GLboolean r700SyncSurf(context_t *context,
 			      struct radeon_bo *pbo,
 			      uint32_t read_domain,
 			      uint32_t write_domain,
 			      uint32_t sync_type);
 
-extern int       r700SetupStreams(GLcontext * ctx);
-extern void      r700SetupVTXConstants(GLcontext  * ctx, 
-				       unsigned int nStreamID,
-				       void *       pAos,
-				       unsigned int size,      /* number of elements in vector */
-				       unsigned int stride,
-				       unsigned int Count);    /* number of vectors in stream */
-
+extern void r700SetupStreams(GLcontext * ctx);
+extern void r700Start3D(context_t *context);
 extern void r600InitAtoms(context_t *context);
 
 #define RADEON_D_CAPTURE 0
diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c
index b0c7294682a..be86de170f9 100644
--- a/src/mesa/drivers/dri/r600/r600_emit.c
+++ b/src/mesa/drivers/dri/r600/r600_emit.c
@@ -51,53 +51,55 @@ void r600EmitCacheFlush(context_t *rmesa)
 {
 }
 
-GLboolean r600EmitShader(GLcontext * ctx, 
+GLboolean r600EmitShader(GLcontext * ctx,
                          void ** shaderbo,
-			             GLvoid * data, 
+			 GLvoid * data,
                          int sizeinDWORD,
-                         char * szShaderUsage) 
+                         char * szShaderUsage)
 {
-    radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
-
-    struct radeon_bo * pbo;
-    uint32_t *out;
+	radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
+	struct radeon_bo * pbo;
+	uint32_t *out;
 
 shader_again_alloc:
-    pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
-			 0,
-                         sizeinDWORD * 4,
-                         256,
-                         RADEON_GEM_DOMAIN_GTT,
-			 0);
+	pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
+			     0,
+			     sizeinDWORD * 4,
+			     256,
+			     RADEON_GEM_DOMAIN_GTT,
+			     0);
 
 	if (!pbo) {
 		rcommonFlushCmdBuf(radeonctx, __FUNCTION__);
 		goto shader_again_alloc;
 	}
 
+	radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs,
+					  pbo,
+					  RADEON_GEM_DOMAIN_GTT, 0);
+
         if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs,
                                           pbo,
-                                          RADEON_GEM_DOMAIN_GTT, 0))
+                                          RADEON_GEM_DOMAIN_GTT, 0)) {
                 fprintf(stderr,"failure to revalidate BOs - badness\n");
-
+		return GL_FALSE;
+	}
 
 	radeon_bo_map(pbo, 1);
 
-    radeon_bo_ref(pbo);
-
-    out = (uint32_t*)(pbo->ptr);
+	out = (uint32_t*)(pbo->ptr);
 
-    memcpy(out, data, sizeinDWORD * 4);
+	memcpy(out, data, sizeinDWORD * 4);
 
-    radeon_bo_unmap(pbo); 
+	radeon_bo_unmap(pbo);
 
-    *shaderbo = (void*)pbo;
+	*shaderbo = (void*)pbo;
 
-    return GL_TRUE;
+	return GL_TRUE;
 }
 
-GLboolean r600DeleteShader(GLcontext * ctx, 
-                           void * shaderbo) 
+GLboolean r600DeleteShader(GLcontext * ctx,
+                           void * shaderbo)
 {
     struct radeon_bo * pbo = (struct radeon_bo *)shaderbo;
 
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 1057d7d8bbf..9f1bf45246f 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -60,6 +60,10 @@ void r600UpdateTextureState(GLcontext * ctx)
 	struct radeon_tex_obj *t;
 	GLuint    unit;
 
+	R600_STATECHANGE(context, tx);
+	R600_STATECHANGE(context, tx_smplr);
+	R600_STATECHANGE(context, tx_brdr_clr);
+
 	for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
 		texUnit = &ctx->Texture.Unit[unit];
 		t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 2d68f021dfc..3f11cf2c981 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -41,75 +41,102 @@
 
 #include "radeon_mipmap_tree.h"
 
-GLboolean r700SendTextureState(context_t *context)
+static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
-    unsigned int i;
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    struct radeon_bo *bo = NULL;
-    BATCH_LOCALS(&context->radeon);
+	context_t         *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	struct radeon_bo *bo = NULL;
+	unsigned int i;
+	BATCH_LOCALS(&context->radeon);
 
-    for (i=0; i<R700_TEXTURE_NUMBERUNITS; i++) {
-	    radeonTexObj *t = r700->textures[i];
-	    if (t) {
-		    if (!t->image_override)
-			    bo = t->mt->bo;
-		    else
-			    bo = t->bo;
-		    if (bo) {
-
-			    r700SyncSurf(context, bo,
-					 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
-					 0, TC_ACTION_ENA_bit);
-
-			    BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
-			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-			    R600_OUT_BATCH(i * 7);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
-			    R600_OUT_BATCH(0); /* r700->textures[i]->SQ_TEX_RESOURCE2 */
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
-			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
-						 bo,
-						 0,
-						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
-						 bo,
-						 r700->textures[i]->SQ_TEX_RESOURCE3,
-						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-			    END_BATCH();
-
-			    BEGIN_BATCH_NO_AUTOSTATE(5);
-			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-			    R600_OUT_BATCH(i * 3);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
-			    END_BATCH();
-
-			    BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
-			    R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
-			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
-			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
-			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
-			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
-			    END_BATCH();
-
-			    COMMIT_BATCH();
-		    }
-	    }
-    }
-    return GL_TRUE;
+	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
+		radeonTexObj *t = r700->textures[i];
+		if (t) {
+			if (!t->image_override)
+				bo = t->mt->bo;
+			else
+				bo = t->bo;
+			if (bo) {
+
+				r700SyncSurf(context, bo,
+					     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
+					     0, TC_ACTION_ENA_bit);
+
+				BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
+				R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+				R600_OUT_BATCH(i * 7);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+				R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+				R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
+						     bo,
+						     0,
+						     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+				R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
+						     bo,
+						     r700->textures[i]->SQ_TEX_RESOURCE3,
+						     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+				END_BATCH();
+				COMMIT_BATCH();
+			}
+		}
+	}
+}
+
+static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t         *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	unsigned int i;
+	BATCH_LOCALS(&context->radeon);
+
+	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
+		radeonTexObj *t = r700->textures[i];
+		if (t) {
+			BEGIN_BATCH_NO_AUTOSTATE(5);
+			R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
+			R600_OUT_BATCH(i * 3);
+			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
+			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
+			R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+			END_BATCH();
+			COMMIT_BATCH();
+		}
+	}
+}
+
+static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t         *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	unsigned int i;
+	BATCH_LOCALS(&context->radeon);
+
+	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
+		radeonTexObj *t = r700->textures[i];
+		if (t) {
+			BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
+			R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
+			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
+			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
+			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
+			R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+			END_BATCH();
+			COMMIT_BATCH();
+		}
+	}
 }
 
-void r700SetupVTXConstants(GLcontext  * ctx,
-			   unsigned int nStreamID,
-			   void *       pAos,
-			   unsigned int size,      /* number of elements in vector */
-			   unsigned int stride,
-			   unsigned int count)     /* number of vectors in stream */
+static void r700SetupVTXConstants(GLcontext  * ctx,
+				  unsigned int nStreamID,
+				  void *       pAos,
+				  unsigned int size,      /* number of elements in vector */
+				  unsigned int stride,
+				  unsigned int count)     /* number of vectors in stream */
 {
     context_t *context = R700_CONTEXT(ctx);
     struct radeon_aos * paos = (struct radeon_aos *)pAos;
@@ -127,6 +154,7 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
+	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 	    r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
     else
@@ -169,19 +197,38 @@ void r700SetupVTXConstants(GLcontext  * ctx,
 
 }
 
-int r700SetupStreams(GLcontext * ctx)
+void r700SetupStreams(GLcontext *ctx)
 {
     context_t         *context = R700_CONTEXT(ctx);
-    BATCH_LOCALS(&context->radeon);
-
-    struct r700_vertex_program *vpc
+     struct r700_vertex_program *vpc
              = (struct r700_vertex_program *)ctx->VertexProgram._Current;
-
     TNLcontext *tnl = TNL_CONTEXT(ctx);
-	struct vertex_buffer *vb = &tnl->vb;
+    struct vertex_buffer *vb = &tnl->vb;
+    unsigned int i, j = 0;
 
-    unsigned int unBit;
+    R600_STATECHANGE(context, vtx);
+
+    for(i=0; i<VERT_ATTRIB_MAX; i++) {
+	    if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
+		    rcommon_emit_vector(ctx,
+					&context->radeon.tcl.aos[j],
+					vb->AttribPtr[i]->data,
+					vb->AttribPtr[i]->size,
+					vb->AttribPtr[i]->stride,
+					vb->Count);
+		    j++;
+	    }
+    }
+    context->radeon.tcl.aos_count = j;
+}
+
+static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+    context_t         *context = R700_CONTEXT(ctx);
+    struct r700_vertex_program *vpc
+             = (struct r700_vertex_program *)ctx->VertexProgram._Current;
     unsigned int i, j = 0;
+    BATCH_LOCALS(&context->radeon);
 
     BEGIN_BATCH_NO_AUTOSTATE(6);
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
@@ -194,31 +241,18 @@ int r700SetupStreams(GLcontext * ctx)
     END_BATCH();
     COMMIT_BATCH();
 
-	for(i=0; i<VERT_ATTRIB_MAX; i++)
-	{
-		unBit = 1 << i;
-		if(vpc->mesa_program.Base.InputsRead & unBit)
-		{
-			rcommon_emit_vector(ctx,
-					    &context->radeon.tcl.aos[j],
-					    vb->AttribPtr[i]->data,
-					    vb->AttribPtr[i]->size,
-					    vb->AttribPtr[i]->stride,
-					    vb->Count);
-
-			/* currently aos are packed */
-			r700SetupVTXConstants(ctx,
-					      i,
-					      (void*)(&context->radeon.tcl.aos[j]),
-					      (unsigned int)context->radeon.tcl.aos[j].components,
-					      (unsigned int)context->radeon.tcl.aos[j].stride * 4,
-					      (unsigned int)context->radeon.tcl.aos[j].count);
-			j++;
-		}
-	}
-	context->radeon.tcl.aos_count = j;
-
-    return R600_FALLBACK_NONE;
+    for(i=0; i<VERT_ATTRIB_MAX; i++) {
+	    if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
+		    /* currently aos are packed */
+		    r700SetupVTXConstants(ctx,
+					  i,
+					  (void*)(&context->radeon.tcl.aos[j]),
+					  (unsigned int)context->radeon.tcl.aos[j].components,
+					  (unsigned int)context->radeon.tcl.aos[j].stride * 4,
+					  (unsigned int)context->radeon.tcl.aos[j].count);
+		    j++;
+	    }
+    }
 }
 
 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
@@ -309,8 +343,9 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
 
 }
 
-GLboolean r700SendPSState(context_t *context)
+static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
+	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	struct radeon_bo * pbo;
 	BATCH_LOCALS(&context->radeon);
@@ -318,7 +353,7 @@ GLboolean r700SendPSState(context_t *context)
 	pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
 
 	if (!pbo)
-		return GL_FALSE;
+		return;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -339,13 +374,11 @@ GLboolean r700SendPSState(context_t *context)
 
 	COMMIT_BATCH();
 
-	r700->ps.dirty = GL_FALSE;
-
-	return GL_TRUE;
 }
 
-GLboolean r700SendVSState(context_t *context)
+static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
+	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	struct radeon_bo * pbo;
 	BATCH_LOCALS(&context->radeon);
@@ -353,7 +386,7 @@ GLboolean r700SendVSState(context_t *context)
 	pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
 
 	if (!pbo)
-		return GL_FALSE;
+		return;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -372,14 +405,11 @@ GLboolean r700SendVSState(context_t *context)
         END_BATCH();
 
 	COMMIT_BATCH();
-
-	r700->vs.dirty = GL_FALSE;
-
-	return GL_TRUE;
 }
 
-GLboolean r700SendFSState(context_t *context)
+static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
+	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	struct radeon_bo * pbo;
 	BATCH_LOCALS(&context->radeon);
@@ -396,7 +426,7 @@ GLboolean r700SendFSState(context_t *context)
 	/* XXX */
 
 	if (!pbo)
-		return GL_FALSE;
+		return;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -416,9 +446,6 @@ GLboolean r700SendFSState(context_t *context)
 
 	COMMIT_BATCH();
 
-	r700->fs.dirty = GL_FALSE;
-
-	return GL_TRUE;
 }
 
 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
@@ -650,17 +677,13 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	BATCH_LOCALS(&context->radeon);
 
-        BEGIN_BATCH_NO_AUTOSTATE(27);
+        BEGIN_BATCH_NO_AUTOSTATE(23);
 	R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
 
 	R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
 	R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
 	R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
 
-	R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
-
 	R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
 	R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
 
@@ -675,15 +698,28 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
 	COMMIT_BATCH();
 }
 
+static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+        BEGIN_BATCH_NO_AUTOSTATE(4);
+	R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
+	R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
+	R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
+
 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	BATCH_LOCALS(&context->radeon);
-	unsigned int ui;
 
 	if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
-		BEGIN_BATCH_NO_AUTOSTATE(14);
+		BEGIN_BATCH_NO_AUTOSTATE(11);
 		R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
 		R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
 		R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
@@ -693,31 +729,50 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
 		R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
 		R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
 		R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
-		/* R600 does not have per-MRT blend */
-		R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
 		END_BATCH();
 	}
 
-	BEGIN_BATCH_NO_AUTOSTATE(22);
+	BEGIN_BATCH_NO_AUTOSTATE(7);
 	R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
 	R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
 	R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
-
-	R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
-	R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
-	R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
-
 	R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
-	R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
 
+static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+	BEGIN_BATCH_NO_AUTOSTATE(6);
 	R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
 	R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
 	R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
 	R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
 	R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
 	END_BATCH();
+	COMMIT_BATCH();
+}
+
+static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+	unsigned int ui;
+
+	if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
+		BEGIN_BATCH_NO_AUTOSTATE(3);
+		R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
+		END_BATCH();
+	}
+
+	BEGIN_BATCH_NO_AUTOSTATE(3);
+	R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
+	END_BATCH();
 
 	if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
 		for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
@@ -731,7 +786,22 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
 	}
 
 	COMMIT_BATCH();
+}
 
+static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+	BEGIN_BATCH_NO_AUTOSTATE(6);
+	R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
+	R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
+	R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
+	R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
+	R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
 }
 
 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
@@ -740,25 +810,33 @@ static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	BATCH_LOCALS(&context->radeon);
 
-	BEGIN_BATCH_NO_AUTOSTATE(19);
+	BEGIN_BATCH_NO_AUTOSTATE(9);
 	R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
-
 	R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
 	R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
 	R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
 	R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
 	R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+
+}
+
+static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
 
+	BEGIN_BATCH_NO_AUTOSTATE(10);
 	R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
-
 	R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
 	R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
-
 	END_BATCH();
 	COMMIT_BATCH();
 
@@ -770,35 +848,43 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	BATCH_LOCALS(&context->radeon);
 
-	BEGIN_BATCH_NO_AUTOSTATE(18);
+	BEGIN_BATCH_NO_AUTOSTATE(12);
 	R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
 	R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
 	R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
 	R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
 
+static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+	BEGIN_BATCH_NO_AUTOSTATE(6);
 	R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
 	R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
 	R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
 	R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
 	R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
-
 	END_BATCH();
 	COMMIT_BATCH();
 }
 
-// XXX need to split this up
-static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	BATCH_LOCALS(&context->radeon);
 
-	BEGIN_BATCH_NO_AUTOSTATE(47);
+	BEGIN_BATCH_NO_AUTOSTATE(22);
 	R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
 	R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
 	R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
 
-	R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 13);
+	R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
 	R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
 	R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
 	R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
@@ -811,21 +897,89 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
 	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
 	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
 	R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
-	R600_OUT_BATCH(r700->PA_SC_EDGERULE.u32All);
 
 	R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
 	R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
 	R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
 
+static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+	BEGIN_BATCH_NO_AUTOSTATE(15);
+	R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
+
+static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+
+	BEGIN_BATCH_NO_AUTOSTATE(12);
 	R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
 	R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
+	END_BATCH();
+	COMMIT_BATCH();
+}
+
+static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	int i;
+	BATCH_LOCALS(&context->radeon);
+
+	if (r700->ps.num_consts == 0)
+		return;
 
+	BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
+	R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
+	/* assembler map const from very beginning. */
+	R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
+	for (i = 0; i < r700->ps.num_consts; i++) {
+		R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
+		R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
+		R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
+		R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
+	}
+	END_BATCH();
+	COMMIT_BATCH();
+}
+
+static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	int i;
+	BATCH_LOCALS(&context->radeon);
+
+	if (r700->vs.num_consts == 0)
+		return;
+
+	BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
+	R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
+	/* assembler map const from very beginning. */
+	R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
+	for (i = 0; i < r700->vs.num_consts; i++) {
+		R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
+		R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
+		R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
+		R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
+	}
 	END_BATCH();
 	COMMIT_BATCH();
 }
@@ -835,39 +989,94 @@ static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 	return atom->cmd_size;
 }
 
-#define ALLOC_STATE( ATOM, SZ, EMIT )					\
+static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+
+	return context->radeon.tcl.aos_count * 18;
+}
+
+static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	unsigned int i, count = 0;
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
+		radeonTexObj *t = r700->textures[i];
+		if (t)
+			count++;
+	}
+	return count * 31;
+}
+
+static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	return 2 + (r700->ps.num_consts * 4);
+}
+
+static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	return 2 + (r700->vs.num_consts * 4);
+}
+
+#define ALLOC_STATE( ATOM, CHK, SZ, EMIT )				\
 do {									\
-      context->atoms.ATOM.cmd_size = (SZ);					\
-      context->atoms.ATOM.cmd = NULL;					\
-      context->atoms.ATOM.name = #ATOM;					\
-      context->atoms.ATOM.idx = 0;						\
-      context->atoms.ATOM.check = check_always;				\
-      context->atoms.ATOM.dirty = GL_FALSE;				\
-      context->atoms.ATOM.emit = (EMIT);					\
-      context->radeon.hw.max_state_size += (SZ);			\
-      insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
+	context->atoms.ATOM.cmd_size = (SZ);				\
+	context->atoms.ATOM.cmd = NULL;					\
+	context->atoms.ATOM.name = #ATOM;				\
+	context->atoms.ATOM.idx = 0;					\
+	context->atoms.ATOM.check = check_##CHK;			\
+	context->atoms.ATOM.dirty = GL_FALSE;				\
+	context->atoms.ATOM.emit = (EMIT);				\
+	context->radeon.hw.max_state_size += (SZ);			\
+	insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
 } while (0)
 
 void r600InitAtoms(context_t *context)
 {
+	context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
 
 	/* Setup the atom linked list */
 	make_empty_list(&context->radeon.hw.atomlist);
 	context->radeon.hw.atomlist.name = "atom-list";
 
-	ALLOC_STATE(sq, 34, r700SendSQConfig);
-	ALLOC_STATE(db, 27, r700SendDBState);
-	ALLOC_STATE(db_target, 19, r700SendDepthTargetState);
-	ALLOC_STATE(sc, 47, r700SendSCState);
-	ALLOC_STATE(cl, 18, r700SendCLState);
-	ALLOC_STATE(ucp, 36, r700SendUCPState);
-	ALLOC_STATE(su, 19, r700SendSUState);
-	ALLOC_STATE(cb, 39, r700SendCBState);
-	ALLOC_STATE(cb_target, 32, r700SendRenderTargetState);
-	ALLOC_STATE(sx, 9, r700SendSXState);
-	ALLOC_STATE(vgt, 41, r700SendVGTState);
-	ALLOC_STATE(spi, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
-	ALLOC_STATE(vpt, 16, r700SendViewportState);
+	ALLOC_STATE(sq, always, 34, r700SendSQConfig);
+	ALLOC_STATE(db, always, 23, r700SendDBState);
+	ALLOC_STATE(stencil, always, 4, r700SendStencilState);
+	ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
+	ALLOC_STATE(sc, always, 15, r700SendSCState);
+	ALLOC_STATE(scissor, always, 22, r700SendScissorState);
+	ALLOC_STATE(aa, always, 12, r700SendAAState);
+	ALLOC_STATE(cl, always, 12, r700SendCLState);
+	ALLOC_STATE(gb, always, 6, r700SendGBState);
+	ALLOC_STATE(ucp, always, 36, r700SendUCPState);
+	ALLOC_STATE(su, always, 9, r700SendSUState);
+	ALLOC_STATE(poly, always, 10, r700SendPolyState);
+	ALLOC_STATE(cb, always, 18, r700SendCBState);
+	ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
+	ALLOC_STATE(blnd, always, 30, r700SendCBBlendState);
+	ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
+	ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
+	ALLOC_STATE(sx, always, 9, r700SendSXState);
+	ALLOC_STATE(vgt, always, 41, r700SendVGTState);
+	ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
+	ALLOC_STATE(vpt, always, 16, r700SendViewportState);
+	ALLOC_STATE(fs, always, 18, r700SendFSState);
+	ALLOC_STATE(vs, always, 18, r700SendVSState);
+	ALLOC_STATE(ps, always, 21, r700SendPSState);
+	ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
+	ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
+	ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
+	ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
+	ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
+	ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
 
 	context->radeon.hw.is_dirty = GL_TRUE;
 	context->radeon.hw.all_dirty = GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index c0ec4b0dd59..ae249e15fd4 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -46,6 +46,7 @@
 #define R700_MAX_VIEWPORTS       16
 #define R700_MAX_SHADER_EXPORTS  32
 #define R700_MAX_UCP             6
+#define R700_MAX_DX9_CONSTS      256
 
 /* Enum not show in r600_*.h */
 
@@ -224,6 +225,8 @@ typedef struct _PS_STATE_STRUCT
 	union UINT_FLOAT         	SQ_PGM_EXPORTS_PS         ;  /* 0xA215 */
 	union UINT_FLOAT       	        SQ_PGM_CF_OFFSET_PS       ;  /* 0xA233 */
 	GLboolean                         dirty;
+	int                             num_consts;
+	union UINT_FLOAT                consts[R700_MAX_DX9_CONSTS][4];
 } PS_STATE_STRUCT;
 
 typedef struct _VS_STATE_STRUCT
@@ -232,6 +235,8 @@ typedef struct _VS_STATE_STRUCT
 	union UINT_FLOAT  		SQ_PGM_RESOURCES_VS       ;  /* 0xA21A */
 	union UINT_FLOAT       	        SQ_PGM_CF_OFFSET_VS       ;  /* 0xA234 */
 	GLboolean                         dirty;
+	int                             num_consts;
+	union UINT_FLOAT                consts[R700_MAX_DX9_CONSTS][4];
 } VS_STATE_STRUCT;
 
 typedef struct _GS_STATE_STRUCT
diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index 6249bde6f18..098b420dfcc 100644
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -270,7 +270,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    BATCH_LOCALS(&context->radeon);
     struct r700_fragment_program *fp = (struct r700_fragment_program *)
 	                                   (ctx->FragmentProgram._Current);
     r700_AssemblerBase         *pAsm = &(fp->r700AsmCode);
@@ -280,6 +279,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
     unsigned int ui, i;
     unsigned int unNumOfReg;
     unsigned int unBit;
+    GLuint exportCount;
 
     if(GL_FALSE == fp->loaded)
     {
@@ -305,8 +305,15 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
     (context->chipobj.MemUse)(context, fp->shadercode.buf->id);
     */
 
+    R600_STATECHANGE(context, ps);
+
+    r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
+    SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
+
     r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */
 
+    R600_STATECHANGE(context, spi);
+
     unNumOfReg = fp->r700Shader.nRegs + 1;
 
     ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
@@ -323,8 +330,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 
     ui = (unNumOfReg < ui) ? ui : unNumOfReg;
 
-    SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); 
-    
+    SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
+
     CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
 
     if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
@@ -336,6 +343,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
     SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
              EXPORT_MODE_shift, EXPORT_MODE_mask);
 
+    R600_STATECHANGE(context, db);
+
     if(fp->r700Shader.killIsUsed)
     {
 	    SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
@@ -347,42 +356,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 
     if(fp->r700Shader.depthIsExported)
     {
-	    SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); 
+	    SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
     }
     else
     {
         CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
     }
 
-    /* sent out shader constants. */
-    paramList = fp->mesa_program.Base.Parameters;
-
-    if(NULL != paramList)
-    {
-        _mesa_load_state_parameters(ctx, paramList);
-
-        unNumParamData = paramList->NumParameters * 4;
-
-        BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData);
-
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
-
-        /* assembler map const from very beginning. */
-        R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
-
-        unNumParamData = paramList->NumParameters;
-
-        for(ui=0; ui<unNumParamData; ui++)
-        {
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
-        }
-        END_BATCH();
-        COMMIT_BATCH();
-    }
-
     // emit ps input map
     unBit = 1 << FRAG_ATTRIB_WPOS;
     if(mesa_fp->Base.InputsRead & unBit)
@@ -449,6 +429,34 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 	    }
     }
 
+    R600_STATECHANGE(context, cb);
+    exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
+    r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
+
+    /* sent out shader constants. */
+    paramList = fp->mesa_program.Base.Parameters;
+
+    if(NULL != paramList) {
+	    _mesa_load_state_parameters(ctx, paramList);
+
+	    if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
+		    return GL_FALSE;
+
+	    R600_STATECHANGE(context, ps_consts);
+
+	    r700->ps.num_consts = paramList->NumParameters;
+
+	    unNumParamData = paramList->NumParameters;
+
+	    for(ui=0; ui<unNumParamData; ui++) {
+		    r700->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
+		    r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
+		    r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
+		    r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
+	    }
+    } else
+	    r700->ps.num_consts = 0;
+
     return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index f0cd357c765..c8b405f5557 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -55,7 +55,6 @@
 
 void r700WaitForIdle(context_t *context);
 void r700WaitForIdleClean(context_t *context);
-void r700Start3D(context_t *context);
 GLboolean r700SendTextureState(context_t *context);
 static unsigned int r700PrimitiveType(int prim);
 void r600UpdateTextureState(GLcontext * ctx);
@@ -116,39 +115,6 @@ void r700Start3D(context_t *context)
     r700WaitForIdleClean(context);
 }
 
-static GLboolean r700SetupShaders(GLcontext * ctx)
-{
-    context_t *context = R700_CONTEXT(ctx);
-
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
-    GLuint exportCount;
-
-    r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
-    r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
-
-    SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-    SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-
-    r700SetupVertexProgram(ctx);
-
-    r700SetupFragmentProgram(ctx);
-
-    exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
-    r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
-
-    r600UpdateTextureState(ctx);
-
-    r700SendFSState(context); // FIXME just a place holder for now
-    r700SendPSState(context);
-    r700SendVSState(context);
-
-    r700SendTextureState(context);
-    r700SetupStreams(ctx);
-
-    return GL_TRUE;
-}
-
 GLboolean r700SyncSurf(context_t *context,
 		       struct radeon_bo *pbo,
 		       uint32_t read_domain,
@@ -333,7 +299,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
 }
 
 static GLboolean r700RunRender(GLcontext * ctx,
-			                   struct tnl_pipeline_stage *stage)
+			       struct tnl_pipeline_stage *stage)
 {
     context_t *context = R700_CONTEXT(ctx);
     radeonContextPtr radeon = &context->radeon;
@@ -347,12 +313,15 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     /* just an estimate, need to properly calculate this */
     rcommonEnsureCmdBufSpace(&context->radeon,
-			     radeon->hw.max_state_size + ind_count + 1000, __FUNCTION__);
+			     radeon->hw.max_state_size + ind_count, __FUNCTION__);
 
-    r700Start3D(context);
     r700UpdateShaders(ctx);
     r700SetScissor(context);
-    r700SetupShaders(ctx);
+    r700SetupVertexProgram(ctx);
+    r700SetupFragmentProgram(ctx);
+    r600UpdateTextureState(ctx);
+    r700SetupStreams(ctx);
+
     radeonEmitState(radeon);
 
     /* richard test code */
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 6b44cc0ceb6..75b2b72eb93 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -168,7 +168,6 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
 {
 	context_t *context = R700_CONTEXT(ctx);
-	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
 	R600_STATECHANGE(context, cb_target);
 	R600_STATECHANGE(context, db_target);
@@ -400,7 +399,7 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //-------------
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
-	R600_STATECHANGE(context, cb);
+	R600_STATECHANGE(context, blnd_clr);
 
 	r700->CB_BLEND_RED.f32All = cf[0];
 	r700->CB_BLEND_GREEN.f32All = cf[1];
@@ -470,7 +469,7 @@ static void r700SetBlendState(GLcontext * ctx)
 	int id = 0;
 	uint32_t blend_reg = 0, eqn, eqnA;
 
-	R600_STATECHANGE(context, cb);
+	R600_STATECHANGE(context, blnd);
 
 	if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
 		SETfield(blend_reg,
@@ -661,7 +660,7 @@ static void r700SetLogicOpState(GLcontext *ctx)
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
 
-	R600_STATECHANGE(context, cb);
+	R600_STATECHANGE(context, blnd);
 
 	if (RGBA_LOGICOP_ENABLED(ctx))
 		SETfield(r700->CB_COLOR_CONTROL.u32All,
@@ -1024,7 +1023,7 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
 	//fixme
 	//r300CatchStencilFallback(ctx);
 
-	R600_STATECHANGE(context, db);
+	R600_STATECHANGE(context, stencil);
 
 	//front
 	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
@@ -1055,7 +1054,7 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) /
 	//fixme
 	//r300CatchStencilFallback(ctx);
 
-	R600_STATECHANGE(context, db);
+	R600_STATECHANGE(context, stencil);
 
 	// front
 	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
@@ -1215,7 +1214,7 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //
 
 	factor *= 12.0;
 
-	R600_STATECHANGE(context, su);
+	R600_STATECHANGE(context, poly);
 
 	r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
 	r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
@@ -1356,7 +1355,7 @@ void r700SetScissor(context_t *context) //---------------
 		y2 = rrb->dPriv->y + rrb->dPriv->h;
 	}
 
-	R600_STATECHANGE(context, sc);
+	R600_STATECHANGE(context, scissor);
 
 	/* window */
 	SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
@@ -1422,7 +1421,6 @@ static void r700SetRenderTarget(context_t *context, int id)
 
     rrb = radeon_get_colorbuffer(&context->radeon);
     if (!rrb || !rrb->bo) {
-	    fprintf(stderr, "no rrb\n");
 	    return;
     }
 
@@ -1579,6 +1577,7 @@ static void r700InitSQConfig(GLcontext * ctx)
     case CHIP_FAMILY_RV610:
     case CHIP_FAMILY_RV620:
     case CHIP_FAMILY_RS780:
+    case CHIP_FAMILY_RS880:
     default:
 	    num_ps_gprs = 84;
 	    num_vs_gprs = 36;
@@ -1661,6 +1660,7 @@ static void r700InitSQConfig(GLcontext * ctx)
     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
+	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 	    CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
     else
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index 31e71cdfa30..550594e9df8 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -336,7 +336,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    BATCH_LOCALS(&context->radeon);
     struct r700_vertex_program *vp
              = (struct r700_vertex_program *)ctx->VertexProgram._Current;
 
@@ -368,8 +367,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
     (context->chipobj.MemUse)(context, vp->shadercode.buf->id);
     */
 
-    r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ 
-    
+    R600_STATECHANGE(context, vs);
+    R600_STATECHANGE(context, fs); /* hack */
+
+    r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
+    SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
+
+    r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */
+
     SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
              NUM_GPRS_shift, NUM_GPRS_mask);
 
@@ -379,9 +384,12 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
                  STACK_SIZE_shift, STACK_SIZE_mask);
     }
 
-    SETfield(r700->SPI_VS_OUT_CONFIG.u32All, vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
+    R600_STATECHANGE(context, spi);
+
+    SETfield(r700->SPI_VS_OUT_CONFIG.u32All,
+	     vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
              VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask);
-	SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
+    SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
              NUM_INTERP_shift, NUM_INTERP_mask);
 
     /*
@@ -392,34 +400,26 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
     /* sent out shader constants. */
     paramList = vp->mesa_program.Base.Parameters;
 
-    if(NULL != paramList)
-    {
-        _mesa_load_state_parameters(ctx, paramList);
+    if(NULL != paramList) {
+	    _mesa_load_state_parameters(ctx, paramList);
 
-        unNumParamData = paramList->NumParameters * 4;
+	    if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
+		    return GL_FALSE;
 
-        BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2);
+	    R600_STATECHANGE(context, vs_consts);
 
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
-        /* assembler map const from very beginning. */
-        R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
+	    r700->vs.num_consts = paramList->NumParameters;
 
-        unNumParamData = paramList->NumParameters;
+	    unNumParamData = paramList->NumParameters;
 
-        for(ui=0; ui<unNumParamData; ui++)
-        {
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
-            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
-        }
-        END_BATCH();
-        COMMIT_BATCH();
-    }
+	    for(ui=0; ui<unNumParamData; ui++) {
+		    r700->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
+		    r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
+		    r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
+		    r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
+	    }
+    } else
+	    r700->vs.num_consts = 0;
 
     return GL_TRUE;
 }
-
-
-
-
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
index 8789e3ab09b..71413716333 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
@@ -73,6 +73,7 @@ struct radeon_bo_funcs {
 			  uint32_t pitch);
     int (*bo_get_tiling)(struct radeon_bo *bo, uint32_t *tiling_flags,
 			  uint32_t *pitch);
+    int (*bo_is_busy)(struct radeon_bo *bo, uint32_t *domain);
 };
 
 struct radeon_bo_manager {
@@ -170,6 +171,15 @@ static inline int _radeon_bo_wait(struct radeon_bo *bo,
     return bo->bom->funcs->bo_wait(bo);
 }
 
+static inline int _radeon_bo_is_busy(struct radeon_bo *bo,
+				     uint32_t *domain,
+                                     const char *file,
+                                     const char *func,
+                                     int line)
+{
+    return bo->bom->funcs->bo_is_busy(bo, domain);
+}
+
 static inline int radeon_bo_set_tiling(struct radeon_bo *bo,
 				       uint32_t tiling_flags, uint32_t pitch)
 {
@@ -203,5 +213,7 @@ static inline int radeon_bo_is_static(struct radeon_bo *bo)
     _radeon_bo_debug(bo, opcode, __FILE__, __FUNCTION__, __LINE__)
 #define radeon_bo_wait(bo) \
     _radeon_bo_wait(bo, __FILE__, __func__, __LINE__)
+#define radeon_bo_is_busy(bo, domain) \
+    _radeon_bo_is_busy(bo, domain, __FILE__, __func__, __LINE__)
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index b1cc155f71a..a10c6b73abc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -542,6 +542,18 @@ static int bo_unmap(struct radeon_bo *bo)
     return 0;
 }
 
+static int bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
+{
+    *domain = 0;
+    if (bo->domains & RADEON_GEM_DOMAIN_GTT)
+        *domain = RADEON_GEM_DOMAIN_GTT;
+    else
+        *domain = RADEON_GEM_DOMAIN_CPU;
+    if (legacy_is_pending(bo))
+        return -EBUSY;
+    else
+        return 0;
+}
 
 static int bo_is_static(struct radeon_bo *bo)
 {
@@ -559,6 +571,7 @@ static struct radeon_bo_funcs bo_legacy_funcs = {
     bo_is_static,
     NULL,
     NULL,
+    bo_is_busy
 };
 
 static int bo_vram_validate(struct radeon_bo *bo,
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index a275c8fb143..0da1c0f9ee3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -335,6 +335,12 @@
 #define PCI_CHIP_RS780_9615             0x9615
 #define PCI_CHIP_RS780_9616             0x9616
 
+#define PCI_CHIP_RS880_9710             0x9710
+#define PCI_CHIP_RS880_9711             0x9711
+#define PCI_CHIP_RS880_9712             0x9712
+#define PCI_CHIP_RS880_9713             0x9713
+#define PCI_CHIP_RS880_9714             0x9714
+
 #define PCI_CHIP_RV770_9440             0x9440
 #define PCI_CHIP_RV770_9441             0x9441
 #define PCI_CHIP_RV770_9442             0x9442
@@ -421,6 +427,7 @@ enum {
    CHIP_FAMILY_RV620,
    CHIP_FAMILY_RV635,
    CHIP_FAMILY_RS780,
+   CHIP_FAMILY_RS880,
    CHIP_FAMILY_RV770,
    CHIP_FAMILY_RV730,
    CHIP_FAMILY_RV710,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ad4584a2bde..ef296e491eb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -92,6 +92,7 @@ static const char* get_chip_family_name(int chip_family)
 	case CHIP_FAMILY_RV620: return "RV620";
 	case CHIP_FAMILY_RV635: return "RV635";
 	case CHIP_FAMILY_RS780: return "RS780";
+	case CHIP_FAMILY_RS880: return "RS880";
 	case CHIP_FAMILY_RV770: return "RV770";
 	case CHIP_FAMILY_RV730: return "RV730";
 	case CHIP_FAMILY_RV710: return "RV710";
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
index ee403d173cc..ab4eca31a3c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
@@ -201,6 +201,15 @@ static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword)
     }
 }
 
+static inline void radeon_cs_write_table(struct radeon_cs *cs, void *data, uint32_t size)
+{
+    memcpy(cs->packets + cs->cdw, data, size * 4);
+    cs->cdw += size;
+    if (cs->section) {
+	    cs->section_cdw += size;
+    }
+}
+
 static inline void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data)
 {
     cs->space_flush_fn = fn;
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 7e8f50e3df2..f306befec47 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -30,6 +30,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 **************************************************************************/
 
+#include <errno.h>
 #include "radeon_common.h"
 #include "main/simple_list.h"
 
@@ -302,7 +303,13 @@ void radeonReturnDmaRegion(radeonContextPtr rmesa, int return_bytes)
 
 static int radeon_bo_is_idle(struct radeon_bo* bo)
 {
-	return bo->cref == 1;
+	uint32_t domain;
+	int ret = radeon_bo_is_busy(bo, &domain);
+	if (ret == -EINVAL) {
+		WARN_ONCE("Your libdrm or kernel doesn't have support for busy query.\n"
+			"This may cause small performance drop for you.\n");
+	}
+	return ret != -EBUSY;
 }
 
 void radeonReleaseDmaRegions(radeonContextPtr rmesa)
diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
index 70251946dff..7eef4faaf61 100644
--- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c
+++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
@@ -32,7 +32,19 @@
 
 #define DDEBUG 0
 
-#define PAGE_SIZE 4096
+static int radeonQueryIsFlushed(GLcontext *ctx, struct gl_query_object *q)
+{
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+	struct radeon_query_object *tmp, *query = (struct radeon_query_object *)q;
+
+	foreach(tmp, &radeon->query.not_flushed_head) {
+		if (tmp == query) {
+			return 0;
+		}
+	}
+
+	return 1;
+}
 
 static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
 {
@@ -86,22 +98,11 @@ static void radeonDeleteQuery(GLcontext *ctx, struct gl_query_object *q)
 
 static void radeonWaitQuery(GLcontext *ctx, struct gl_query_object *q)
 {
-	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-	struct radeon_query_object *tmp, *query = (struct radeon_query_object *)q;
+	struct radeon_query_object *query = (struct radeon_query_object *)q;
 
 	/* If the cmdbuf with packets for this query hasn't been flushed yet, do it now */
-	{
-		GLboolean found = GL_FALSE;
-		foreach(tmp, &radeon->query.not_flushed_head) {
-			if (tmp == query) {
-				found = GL_TRUE;
-				break;
-			}
-		}
-
-		if (found)
-			ctx->Driver.Flush(ctx);
-	}
+	if (!radeonQueryIsFlushed(ctx, q))
+		ctx->Driver.Flush(ctx);
 
 	if (DDEBUG) fprintf(stderr, "%s: query id %d, bo %p, offset %d\n", __FUNCTION__, q->Id, query->bo, query->curr_offset);
 
@@ -124,7 +125,7 @@ static void radeonBeginQuery(GLcontext *ctx, struct gl_query_object *q)
 		radeon->dma.flush(radeon->glCtx);
 
 	if (!query->bo) {
-		query->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, PAGE_SIZE, PAGE_SIZE, RADEON_GEM_DOMAIN_GTT, 0);
+		query->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, RADEON_QUERY_PAGE_SIZE, RADEON_QUERY_PAGE_SIZE, RADEON_GEM_DOMAIN_GTT, 0);
 	}
 	query->curr_offset = 0;
 
@@ -168,16 +169,32 @@ static void radeonEndQuery(GLcontext *ctx, struct gl_query_object *q)
 	radeon->query.current = NULL;
 }
 
-/**
- * TODO:
- * should check if bo is idle, bo there's no interface to do it
- * just wait for result now
- */
 static void radeonCheckQuery(GLcontext *ctx, struct gl_query_object *q)
 {
 	if (DDEBUG) fprintf(stderr, "%s: query id %d\n", __FUNCTION__, q->Id);
 
+#ifdef DRM_RADEON_GEM_BUSY
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+
+	if (radeon->radeonScreen->kernel_mm) {
+		struct radeon_query_object *query = (struct radeon_query_object *)q;
+		uint32_t domain;
+
+		/* Need to perform a flush, as per ARB_occlusion_query spec */
+		if (!radeonQueryIsFlushed(ctx, q)) {
+			ctx->Driver.Flush(ctx);
+		}
+
+		if (radeon_bo_is_busy(query->bo, &domain) == 0) {
+			radeonQueryGetResult(ctx, q);
+			query->Base.Ready = GL_TRUE;
+		}
+	} else {
+		radeonWaitQuery(ctx, q);
+	}
+#else
 	radeonWaitQuery(ctx, q);
+#endif
 }
 
 void radeonInitQueryObjFunctions(struct dd_function_table *functions)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index e28543d855a..10afe527d3d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -853,6 +853,14 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
       screen->chip_family = CHIP_FAMILY_RS780;
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
+   case PCI_CHIP_RS880_9710:
+   case PCI_CHIP_RS880_9711:
+   case PCI_CHIP_RS880_9712:
+   case PCI_CHIP_RS880_9713:
+   case PCI_CHIP_RS880_9714:
+      screen->chip_family = CHIP_FAMILY_RS880;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
+      break;
 
    case PCI_CHIP_RV770_9440:
    case PCI_CHIP_RV770_9441:
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index e70dbbe06f2..bed3935130b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -876,7 +876,7 @@ void radeonInitState( r100ContextPtr rmesa )
       rmesa->hw.glt.emit = vec_emit;
       rmesa->hw.eye.emit = vec_emit;
       
-      for (i = 0; i <= 6; i++)
+      for (i = 0; i < 6; i++)
 	 rmesa->hw.mat[i].emit = vec_emit;
 
       for (i = 0; i < 8; i++)