intel: use intel_rb_format() to get renderbuffer format

This will make future changes cleaner and less invasive.

11 files changed, 56 insertions, 42 deletions

diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 513acb938f1..082372e2c5d 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -642,7 +642,7 @@ i830_set_draw_region(struct intel_context *intel,
             DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z);    /* .5 */
 
    if (irb != NULL) {
-      value |= i830_render_target_format_for_mesa_format[irb->Base.Format];
+      value |= i830_render_target_format_for_mesa_format[intel_rb_format(irb)];
    }
 
    if (depth_region && depth_region->cpp == 4) {
@@ -803,7 +803,7 @@ i830_update_draw_buffer(struct intel_context *intel)
 
    /* Check for stencil fallback. */
    if (irbStencil && irbStencil->mt) {
-      assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
+      assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
    } else if (irbStencil && !irbStencil->mt) {
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
@@ -816,7 +816,7 @@ i830_update_draw_buffer(struct intel_context *intel)
     * we still need to set up the shared depth/stencil state so we can use it.
     */
    if (depthRegion == NULL && irbStencil && irbStencil->mt
-       && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
+       && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
       depthRegion = irbStencil->mt->region;
    }
 
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index e938af84bf5..62bfa0abf49 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -607,7 +607,7 @@ i915_set_draw_region(struct intel_context *intel,
             DSTORG_VERT_BIAS(0x8) |     /* .5 */
             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
    if (irb != NULL) {
-      value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
+      value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
    } else {
       value |= DV_PF_8888;
    }
@@ -775,7 +775,7 @@ i915_update_draw_buffer(struct intel_context *intel)
 
    /* Check for stencil fallback. */
    if (irbStencil && irbStencil->mt) {
-      assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
+      assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
    } else if (irbStencil && !irbStencil->mt) {
       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
@@ -788,7 +788,7 @@ i915_update_draw_buffer(struct intel_context *intel)
     * we still need to set up the shared depth/stencil state so we can use it.
     */
    if (depthRegion == NULL && irbStencil && irbStencil->mt
-       && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
+       && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
       depthRegion = irbStencil->mt->region;
    }
 
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1a7d3282472..68e1e80d3b3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -209,8 +209,8 @@ brw_depthbuffer_format(struct brw_context *brw)
    if (!drb &&
        (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
        !srb->mt->stencil_mt &&
-       (srb->Base.Format == MESA_FORMAT_S8_Z24 ||
-	srb->Base.Format == MESA_FORMAT_Z32_FLOAT_X24S8)) {
+       (intel_rb_format(srb) == MESA_FORMAT_S8_Z24 ||
+	intel_rb_format(srb) == MESA_FORMAT_Z32_FLOAT_X24S8)) {
       drb = srb;
    }
 
@@ -246,7 +246,7 @@ brw_depthbuffer_format(struct brw_context *brw)
       return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
    default:
       _mesa_problem(ctx, "Unexpected depth format %s\n",
-		    _mesa_get_format_name(drb->Base.Format));
+		    _mesa_get_format_name(intel_rb_format(drb)));
       return BRW_DEPTHFORMAT_D16_UNORM;
    }
 }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ef270e78b25..7fd83ea984c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -906,24 +906,25 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    uint32_t *surf;
    uint32_t tile_x, tile_y;
    uint32_t format = 0;
+   gl_format rb_format = intel_rb_format(irb);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 			  6 * 4, 32, &brw->bind.surf_offset[unit]);
 
-   switch (irb->Base.Format) {
+   switch (rb_format) {
    case MESA_FORMAT_SARGB8:
       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 	 surfaces to the blend/update as sRGB */
       if (ctx->Color.sRGBEnabled)
-	 format = brw_format_for_mesa_format(irb->Base.Format);
+	 format = brw_format_for_mesa_format(rb_format);
       else
 	 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
       break;
    default:
-      format = brw->render_target_format[irb->Base.Format];
-      if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
+      format = brw->render_target_format[rb_format];
+      if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 	 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-		       __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
+		       __FUNCTION__, _mesa_get_format_name(rb_format));
       }
       break;
    }
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 70a0bc986e2..d429adcfd60 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -200,6 +200,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct intel_region *region = irb->mt->region;
    struct gen7_surface_state *surf;
    uint32_t tile_x, tile_y;
+   gl_format rb_format = intel_rb_format(irb);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 			  sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
@@ -210,21 +211,21 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    if (irb->mt->align_w == 8)
       surf->ss0.horizontal_alignment = 1;
 
-   switch (irb->Base.Format) {
+   switch (rb_format) {
    case MESA_FORMAT_SARGB8:
       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 	 surfaces to the blend/update as sRGB */
       if (ctx->Color.sRGBEnabled)
-	 surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
+	 surf->ss0.surface_format = brw_format_for_mesa_format(rb_format);
       else
 	 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
       break;
    default:
-      assert(brw_render_target_supported(intel, irb->Base.Format));
-      surf->ss0.surface_format = brw->render_target_format[irb->Base.Format];
-      if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
+      assert(brw_render_target_supported(intel, rb_format));
+      surf->ss0.surface_format = brw->render_target_format[rb_format];
+      if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 	 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-		       __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
+		       __FUNCTION__, _mesa_get_format_name(rb_format));
       }
        break;
    }
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index e484fd34bfd..9eacadd213c 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -328,7 +328,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 
 	 _mesa_unclamped_float_rgba_to_ubyte(clear, color);
 
-	 switch (irb->Base.Format) {
+	 switch (intel_rb_format(irb)) {
 	 case MESA_FORMAT_ARGB8888:
 	 case MESA_FORMAT_XRGB8888:
 	    clear_val = PACK_COLOR_8888(clear[3], clear[0],
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index ecc03a21be5..30a01bb48f4 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -225,7 +225,7 @@ intel_flush_front(struct gl_context *ctx)
 static unsigned
 intel_bits_per_pixel(const struct intel_renderbuffer *rb)
 {
-   return _mesa_get_format_bytes(rb->Base.Format) * 8;
+   return _mesa_get_format_bytes(intel_rb_format(rb)) * 8;
 }
 
 static void
@@ -1066,7 +1066,7 @@ intel_process_dri2_buffer_no_separate_stencil(struct intel_context *intel,
 
       rb->mt = intel_miptree_create_for_region(intel,
                                                GL_TEXTURE_2D,
-                                               rb->Base.Format,
+                                               intel_rb_format(rb),
                                                region);
       intel_region_release(&region);
       if (!rb->mt)
@@ -1163,7 +1163,7 @@ intel_query_dri2_buffers_with_separate_stencil(struct intel_context *intel,
       (*attachments)[i++] = __DRI_BUFFER_DEPTH;
       (*attachments)[i++] = intel_bits_per_pixel(depth_rb);
 
-      if (intel->vtbl.is_hiz_depth_format(intel, depth_rb->Base.Format)) {
+      if (intel->vtbl.is_hiz_depth_format(intel, intel_rb_format(depth_rb))) {
 	 /* Depth and hiz buffer have same bpp. */
 	 (*attachments)[i++] = __DRI_BUFFER_HIZ;
 	 (*attachments)[i++] = intel_bits_per_pixel(depth_rb);
@@ -1171,7 +1171,7 @@ intel_query_dri2_buffers_with_separate_stencil(struct intel_context *intel,
    }
 
    if (stencil_rb) {
-      assert(stencil_rb->Base.Format == MESA_FORMAT_S8);
+      assert(intel_rb_format(stencil_rb) == MESA_FORMAT_S8);
       (*attachments)[i++] = __DRI_BUFFER_STENCIL;
       (*attachments)[i++] = intel_bits_per_pixel(stencil_rb);
    }
@@ -1283,7 +1283,7 @@ intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
    struct intel_mipmap_tree *mt =
       intel_miptree_create_for_region(intel,
 				      GL_TEXTURE_2D,
-				      rb->Base.Format,
+				      intel_rb_format(rb),
 				      region);
    intel_region_release(&region);
 
@@ -1366,8 +1366,8 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
        */
       struct intel_renderbuffer *depth_rb =
 	 intel_get_renderbuffer(fb, BUFFER_DEPTH);
-      assert(stencil_rb->Base.Format == MESA_FORMAT_S8);
-      assert(depth_rb && depth_rb->Base.Format == MESA_FORMAT_X8_Z24);
+      assert(intel_rb_format(stencil_rb) == MESA_FORMAT_S8);
+      assert(depth_rb && intel_rb_format(depth_rb) == MESA_FORMAT_X8_Z24);
 
       if (stencil_rb->mt->region->tiling == I915_TILING_NONE) {
 	 /*
@@ -1456,7 +1456,7 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
 	 struct intel_mipmap_tree *mt =
 	       intel_miptree_create_for_region(intel,
 	                                       GL_TEXTURE_2D,
-	                                       depth_stencil_rb->Base.Format,
+	                                       intel_rb_format(depth_stencil_rb),
 	                                       region);
 	 intel_region_release(&region);
 	 if (!mt)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 5463776aeb6..2e400e7d5c5 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -822,16 +822,16 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 	 continue;
       }
 
-      if (!intel->vtbl.render_target_supported(intel, irb->Base.Format)) {
+      if (!intel->vtbl.render_target_supported(intel, intel_rb_format(irb))) {
 	 DBG("Unsupported HW texture/renderbuffer format attached: %s\n",
-	     _mesa_get_format_name(irb->Base.Format));
+	     _mesa_get_format_name(intel_rb_format(irb)));
 	 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
       }
 
 #ifdef I915
-      if (!intel_span_supports_format(irb->Base.Format)) {
+      if (!intel_span_supports_format(intel_rb_format(irb))) {
 	 DBG("Unsupported swrast texture/renderbuffer format attached: %s\n",
-	     _mesa_get_format_name(irb->Base.Format));
+	     _mesa_get_format_name(intel_rb_format(irb)));
 	 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
       }
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index edba8e66226..5a0d865739b 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -115,6 +115,14 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
    return intel_renderbuffer(rb);
 }
 
+
+static INLINE gl_format
+intel_rb_format(const struct intel_renderbuffer *rb)
+{
+   return rb->Base.Format;
+}
+
+
 bool
 intel_framebuffer_has_hiz(struct gl_framebuffer *fb);
 
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
index 2682e152abc..18a807508b3 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
@@ -88,6 +88,7 @@ do_blit_copypixels(struct gl_context * ctx,
    bool flip = false;
    struct intel_renderbuffer *draw_irb = NULL;
    struct intel_renderbuffer *read_irb = NULL;
+   gl_format read_format, draw_format;
 
    /* Update draw buffer bounds */
    _mesa_update_state(ctx);
@@ -128,12 +129,15 @@ do_blit_copypixels(struct gl_context * ctx,
       return false;
    }
 
-   if (draw_irb->Base.Format != read_irb->Base.Format &&
-       !(draw_irb->Base.Format == MESA_FORMAT_XRGB8888 &&
-	 read_irb->Base.Format == MESA_FORMAT_ARGB8888)) {
+   read_format = intel_rb_format(read_irb);
+   draw_format = intel_rb_format(draw_irb);
+
+   if (draw_format != read_format &&
+       !(draw_format == MESA_FORMAT_XRGB8888 &&
+	 read_format == MESA_FORMAT_ARGB8888)) {
       fallback_debug("glCopyPixels() fallback: mismatched formats (%s -> %s\n",
-		     _mesa_get_format_name(read_irb->Base.Format),
-		     _mesa_get_format_name(draw_irb->Base.Format));
+		     _mesa_get_format_name(read_format),
+                     _mesa_get_format_name(draw_format));
       return false;
    }
 
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index b6e29f78de6..8617302856d 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -69,16 +69,16 @@ intel_copy_texsubimage(struct intel_context *intel,
       assert(region);
    }
 
-   copy_supported = intelImage->base.Base.TexFormat == irb->Base.Format;
+   copy_supported = intelImage->base.Base.TexFormat == intel_rb_format(irb);
 
    /* Converting ARGB8888 to XRGB8888 is trivial: ignore the alpha bits */
-   if (irb->Base.Format == MESA_FORMAT_ARGB8888 &&
+   if (intel_rb_format(irb) == MESA_FORMAT_ARGB8888 &&
        intelImage->base.Base.TexFormat == MESA_FORMAT_XRGB8888) {
       copy_supported = true;
    }
 
    /* Converting XRGB8888 to ARGB8888 requires setting the alpha bits to 1.0 */
-   if (irb->Base.Format == MESA_FORMAT_XRGB8888 &&
+   if (intel_rb_format(irb) == MESA_FORMAT_XRGB8888 &&
        intelImage->base.Base.TexFormat == MESA_FORMAT_ARGB8888) {
       copy_supported_with_alpha_override = true;
    }
@@ -88,7 +88,7 @@ intel_copy_texsubimage(struct intel_context *intel,
 	 fprintf(stderr, "%s mismatched formats %s, %s\n",
 		 __FUNCTION__,
 		 _mesa_get_format_name(intelImage->base.Base.TexFormat),
-		 _mesa_get_format_name(irb->Base.Format));
+		 _mesa_get_format_name(intel_rb_format(irb)));
       return false;
    }