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authorKenneth Graunke <[email protected]>2017-11-15 22:40:16 -0800
committerKenneth Graunke <[email protected]>2017-11-16 17:39:01 -0800
commit8f91aa35a54e127b68415376ef2b577ea8fc30f9 (patch)
tree1f32c8df240d1285f582311f5cd36f119049becc /src/mesa/drivers/dri
parent59162c122f29884e555e579ca99f5417bc0f4b33 (diff)
i965: Upload invariant state once at the start of the batch on Gen4-5.
We want to emit invariant state at the start of a render batch. In the past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT (because we don't have hardware contexts), which triggered the brw_invariant_state atom. So, it would be emitted before any 3D drawing. (Technically, there might be some BLT commands in the batch because Gen4-5 have a single combined render/BLT ring, but that should be harmless). With the advent of BLORP, this broke. The first item in a batch might be a BLORP operation, which bypasses the normal draw upload path. So, we need to ensure invariant state happens first. To do that, we just upload it when creating a new batch. On Gen6+ we'd need to worry about whether it's a RENDER or BLT batch, but because we have a combined ring, this approach should work fine on Gen4-5. Seems to fix GPU hangs when playing hardware accelerated video with mpv -hwdec=vaapi on Ironlake. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529 Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/genX_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c4
4 files changed, 3 insertions, 13 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index fd96485d574..94d5c9783db 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -560,15 +560,6 @@ brw_upload_invariant_state(struct brw_context *brw)
ADVANCE_BATCH();
}
-const struct brw_tracked_state brw_invariant_state = {
- .dirty = {
- .mesa = 0,
- .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT,
- },
- .emit = brw_upload_invariant_state
-};
-
/**
* Define the base addresses which some state is referenced from.
*
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index cf13eca3438..ad508950f78 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -51,7 +51,6 @@ extern const struct brw_tracked_state brw_wm_pull_constants;
extern const struct brw_tracked_state brw_cs_pull_constants;
extern const struct brw_tracked_state brw_constant_buffer;
extern const struct brw_tracked_state brw_curbe_offsets;
-extern const struct brw_tracked_state brw_invariant_state;
extern const struct brw_tracked_state brw_binding_table_pointers;
extern const struct brw_tracked_state brw_depthbuffer;
extern const struct brw_tracked_state brw_recalculate_urb_fence;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index d4b0de850c9..112f48181b0 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -5366,8 +5366,6 @@ genX(init_atoms)(struct brw_context *brw)
/* Command packets:
*/
- &brw_invariant_state,
-
&brw_binding_table_pointers,
&genX(blend_constant_color),
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index bbe13f34cef..3412b1d0a5f 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -601,8 +601,10 @@ brw_new_batch(struct brw_context *brw)
* would otherwise be stored in the context (which for all intents and
* purposes means everything).
*/
- if (brw->hw_ctx == 0)
+ if (brw->hw_ctx == 0) {
brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
+ brw_upload_invariant_state(brw);
+ }
brw->ctx.NewDriverState |= BRW_NEW_BATCH;