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authorJason Ekstrand <[email protected]>2016-06-22 16:41:58 -0700
committerJason Ekstrand <[email protected]>2016-08-17 14:46:22 -0700
commit801189e1994a0daa96ff64b9f27a2e14b19cb446 (patch)
tree5b4ef6906192b994e33d93a3da714ff92401c8d7 /src/mesa/drivers/dri
parentb82de88008ddfef051eeccfbc4b36e0e7d47daf3 (diff)
i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing. Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c34
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.h5
2 files changed, 5 insertions, 34 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 5889e95852a..220be8390ae 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -120,34 +120,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
}
-/**
- * Split x_offset and y_offset into a base offset (in bytes) and a remaining
- * x/y offset (in pixels). Note: we can't do this by calling
- * intel_renderbuffer_tile_offsets(), because the offsets may have been
- * adjusted to account for Y vs. W tiling differences. So we compute it
- * directly from the adjusted offsets.
- */
-uint32_t
-brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
- uint32_t *tile_x, uint32_t *tile_y)
-{
- uint32_t mask_x, mask_y;
- uint32_t tiling = info->mt->tiling;
- if (info->map_stencil_as_y_tiled)
- tiling = I915_TILING_Y;
-
- intel_get_tile_masks(tiling, info->mt->tr_mode, info->mt->cpp,
- &mask_x, &mask_y);
-
- *tile_x = info->x_offset & mask_x;
- *tile_y = info->y_offset & mask_y;
-
- return intel_miptree_get_aligned_offset(info->mt, info->x_offset & ~mask_x,
- info->y_offset & ~mask_y,
- info->map_stencil_as_y_tiled);
-}
-
-
void
brw_blorp_params_init(struct brw_blorp_params *params)
{
@@ -354,7 +326,11 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
};
uint32_t offset, tile_x, tile_y;
- offset = brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y);
+ isl_tiling_get_intratile_offset_el(&brw->isl_dev, surf.tiling,
+ isl_format_get_layout(view.format)->bpb / 8,
+ surf.row_pitch,
+ surface->x_offset, surface->y_offset,
+ &offset, &tile_x, &tile_y);
uint32_t surf_offset;
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index e23f48b1a12..06941818aed 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -172,11 +172,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
unsigned int level, unsigned int layer,
mesa_format format, bool is_render_target);
-uint32_t
-brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
- uint32_t *tile_x, uint32_t *tile_y);
-
-
struct brw_blorp_coord_transform
{