diff options
author | Dave Airlie <[email protected]> | 2009-01-22 01:17:31 +1000 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2009-01-22 01:17:31 +1000 |
commit | 674b204ba7c4854fec92a0c939de5012fecb6d87 (patch) | |
tree | 69d6062e160fc47d3f78e5eccc2d4ada6fe85255 /src/mesa/drivers/dri | |
parent | 61bb82636f7b1681b5509e1a9038bbcc1feea35c (diff) |
r200: fix cubemaps
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 26 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_texstate.c | 9 |
2 files changed, 26 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 249f4eb4ce6..26d89432bf0 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -382,6 +382,29 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } +static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r200->state.texture.unit[i].texobj; + GLuint size; + + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 3); + + fprintf(stderr,"total size is %d\n", t->mt->totalsize); + if (t && !t->image_override) { + size = t->mt->totalsize / 6; + OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0); + OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + END_BATCH(); +} /* Initialize the context's hardware state. */ @@ -533,6 +556,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); + for (i = 0; i < 5; i++) + rmesa->hw.cube[i].emit = cube_emit; } else { ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); @@ -542,6 +567,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } + if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) { ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 2a402e99c6f..f8641d18f8d 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1581,11 +1581,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) t->tile_bits = 0; - // if (t->base.Target == GL_TEXTURE_CUBE_MAP) - // t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; - // if (t->base.Target == GL_TEXTURE_3D) - // t->pp_txformat |= R300_TX_FORMAT_3D; - t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK); if (t->base.Target == GL_TEXTURE_3D) { t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); @@ -1628,8 +1623,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { t->pp_txformat |= R200_TXFORMAT_NON_POWER2; - // t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; - } } @@ -1647,8 +1640,6 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object * of the hardware registers). */ setup_hardware_state(rmesa, t); - - if (texObj->Target == GL_TEXTURE_RECTANGLE_NV || texObj->Target == GL_TEXTURE_2D) set_re_cntl_d3d( ctx, unit, GL_FALSE ); |