diff options
author | Brian <[email protected]> | 2007-01-26 18:55:12 -0700 |
---|---|---|
committer | Brian <[email protected]> | 2007-01-26 18:55:12 -0700 |
commit | 1d74e565dbfc1a69c49fe67eed9c91f10d0ad2fc (patch) | |
tree | eecbf78b41dfdea04cac65ce1fa61aad23822148 /src/mesa/drivers/dri | |
parent | 7e85b0a025a82c3ffed060a757a3b4adae03d269 (diff) | |
parent | 5a3d9853958993174f13c8cff6bcf11993a48f65 (diff) |
Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesa
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.c | 53 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.h | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_regions.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_regions.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_screen.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_shader.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_shader.h | 13 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_shader_0.c | 17 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_shader_2.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nouveau_sync.c | 16 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nv40_fragprog.c | 27 | ||||
-rw-r--r-- | src/mesa/drivers/dri/nouveau/nv40_shader.h | 4 |
14 files changed, 110 insertions, 47 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 57ee294f0cf..08741ad90f6 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -414,7 +414,7 @@ GLboolean brw_upload_vertices( struct brw_context *brw, */ while (tmp) { - GLuint i = ffsll(tmp)-1; + GLuint i = _mesa_ffsll(tmp)-1; struct brw_vertex_element *input = &brw->vb.inputs[i]; tmp &= ~((GLuint64EXT)1<<i); diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 459ed109ed5..4486a28adc7 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -61,6 +61,7 @@ #include "bufmgr.h" #include "utils.h" +#include "vblank.h" #ifndef INTEL_DEBUG int INTEL_DEBUG = (0); #endif @@ -86,11 +87,6 @@ int INTEL_DEBUG = (0); int VERBOSE = 0; #endif -#if DEBUG_LOCKING -char *prevLockFile; -int prevLockLine; -#endif - /*************************************** * Mesa's Driver Functions ***************************************/ @@ -184,9 +180,17 @@ const struct dri_extension card_extensions[] = { NULL, NULL } }; -static const struct dri_extension arb_oc_extension = +const struct dri_extension arb_oc_extension = { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}; +void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging) +{ + struct intel_context *intel = ctx?intel_context(ctx):NULL; + driInitExtensions(ctx, card_extensions, enable_imaging); + if (!ctx || intel->intelScreen->drmMinor >= 8) + driInitSingleExtension (ctx, &arb_oc_extension); +} + static const struct dri_debug_control debug_control[] = { { "fall", DEBUG_FALLBACKS }, @@ -248,30 +252,31 @@ static void intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) { struct intel_context *intel = intel_context( ctx ); - GLuint64EXT tmp = 0; drmI830MMIO io = { - .read_write = MMIO_WRITE, + .read_write = MMIO_READ, .reg = MMIO_REGS_PS_DEPTH_COUNT, - .data = &tmp + .data = &q->Result }; - intel->stats_wm = GL_TRUE; + intel->stats_wm++; intelFinish(&intel->ctx); - drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); + drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); } static void intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) { struct intel_context *intel = intel_context( ctx ); + GLuint64EXT tmp; drmI830MMIO io = { .read_write = MMIO_READ, .reg = MMIO_REGS_PS_DEPTH_COUNT, - .data = &q->Result + .data = &tmp }; intelFinish(&intel->ctx); drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); + q->Result = tmp - q->Result; q->Ready = GL_TRUE; - intel->stats_wm = GL_FALSE; + intel->stats_wm--; } @@ -327,6 +332,11 @@ GLboolean intelInitContext( struct intel_context *intel, intel->driScreen = sPriv; intel->sarea = saPriv; + driParseConfigFiles (&intel->optionCache, &intelScreen->optionCache, + intel->driScreen->myNum, "i965"); + + intel->vblank_flags = (intel->intelScreen->irq_active != 0) + ? driGetDefaultVBlankFlags(&intel->optionCache) : VBLANK_FLAG_NO_IRQ; ctx->Const.MaxTextureMaxAnisotropy = 2.0; @@ -409,12 +419,7 @@ GLboolean intelInitContext( struct intel_context *intel, _mesa_printf("IRQs not active. Exiting\n"); exit(1); } - - driInitExtensions( ctx, card_extensions, - GL_TRUE ); - - if (intel->intelScreen->drmMinor >= 8) - driInitSingleExtension (ctx, &arb_oc_extension); + intelInitExtensions(ctx, GL_TRUE); INTEL_DEBUG = driParseDebugString( getenv( "INTEL_DEBUG" ), debug_control ); @@ -441,8 +446,8 @@ GLboolean intelInitContext( struct intel_context *intel, intelScreen->cpp, intelScreen->front.pitch / intelScreen->cpp, intelScreen->height, - intelScreen->front.tiled != 0); /* 0: LINEAR */ - + intelScreen->front.size, + intelScreen->front.tiled != 0); intel->back_region = intel_region_create_static(intel, @@ -452,6 +457,7 @@ GLboolean intelInitContext( struct intel_context *intel, intelScreen->cpp, intelScreen->back.pitch / intelScreen->cpp, intelScreen->height, + intelScreen->back.size, intelScreen->back.tiled != 0); /* Still assuming front.cpp == depth.cpp @@ -468,6 +474,7 @@ GLboolean intelInitContext( struct intel_context *intel, intelScreen->cpp, intelScreen->depth.pitch / intelScreen->cpp, intelScreen->height, + intelScreen->depth.size, intelScreen->depth.tiled != 0); intel_bufferobj_init( intel ); @@ -559,6 +566,9 @@ GLboolean intelMakeCurrent(__DRIcontextPrivate *driContextPriv, if ( intel->driDrawable != driDrawPriv ) { /* Shouldn't the readbuffer be stored also? */ + driDrawableInitVBlank( driDrawPriv, intel->vblank_flags, + &intel->vbl_seq ); + intel->driDrawable = driDrawPriv; intelWindowMoved( intel ); } @@ -693,3 +703,4 @@ void UNLOCK_HARDWARE( struct intel_context *intel ) _glthread_UNLOCK_MUTEX(lockMutex); } + diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index fe7ee382a19..a0f392f9353 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -177,7 +177,7 @@ struct intel_context GLuint second_last_swap_fence; GLboolean aub_wrap; - GLboolean stats_wm; + GLuint stats_wm; struct intel_batchbuffer *batch; @@ -500,6 +500,7 @@ void intelBitmap(GLcontext * ctx, const struct gl_pixelstore_attrib *unpack, const GLubyte * pixels); +void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging); #define _NEW_WINDOW_POS 0x40000000 @@ -522,6 +523,5 @@ static inline struct intel_texture_image *intel_texture_image( struct gl_texture return (struct intel_texture_image *)img; } - #endif diff --git a/src/mesa/drivers/dri/i965/intel_regions.c b/src/mesa/drivers/dri/i965/intel_regions.c index 398b0a0a3b5..835ecdd7257 100644 --- a/src/mesa/drivers/dri/i965/intel_regions.c +++ b/src/mesa/drivers/dri/i965/intel_regions.c @@ -122,10 +122,10 @@ struct intel_region *intel_region_create_static( struct intel_context *intel, GLuint cpp, GLuint pitch, GLuint height, + GLuint size, GLboolean tiled ) { struct intel_region *region = calloc(sizeof(*region), 1); - GLuint size = cpp * pitch * height; GLint pool; DBG("%s\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/i965/intel_regions.h b/src/mesa/drivers/dri/i965/intel_regions.h index 2413f0de33c..d2235f1275b 100644 --- a/src/mesa/drivers/dri/i965/intel_regions.h +++ b/src/mesa/drivers/dri/i965/intel_regions.h @@ -78,6 +78,7 @@ struct intel_region *intel_region_create_static( struct intel_context *intel, GLuint cpp, GLuint pitch, GLuint height, + GLuint size, GLboolean tiled ); /* Map/unmap regions. This is refcounted also: diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 8269deba664..08f0bb340f7 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -38,6 +38,7 @@ #include "intel_screen.h" +#include "intel_context.h" #include "intel_tex.h" #include "intel_span.h" #include "intel_ioctl.h" @@ -61,8 +62,6 @@ const GLuint __driNConfigOptions = 4; static PFNGLXCREATECONTEXTMODES create_context_modes = NULL; #endif /*USE_NEW_INTERFACE*/ -extern const struct dri_extension card_extensions[]; - /** * Map all the memory regions described by the screen. * \return GL_TRUE if success, GL_FALSE if error. @@ -687,7 +686,6 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc (dri_priv->cpp == 2) ? 16 : 24, (dri_priv->cpp == 2) ? 0 : 8, GL_TRUE ); - /* Calling driInitExtensions here, with a NULL context pointer, does not actually * enable the extensions. It just makes sure that all the dispatch offsets for all * the extensions that *might* be enables are known. This is needed because the @@ -696,7 +694,7 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc * * Hello chicken. Hello egg. How are you two today? */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); + intelInitExtensions(NULL, GL_FALSE); } return (void *) psp; diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.c b/src/mesa/drivers/dri/nouveau/nouveau_screen.c index 781ba0113fc..881b20149f0 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_screen.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_screen.c @@ -339,8 +339,12 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc } // temporary lock step versioning - if (drm_expected.patch!=drm_version->patch) + if (drm_expected.patch!=drm_version->patch) { + __driUtilMessage("%s: wrong DRM version, expected %d, got %d\n", + __func__, + drm_expected.patch, drm_version->patch); return NULL; + } psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, ddx_version, dri_version, drm_version, diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.c b/src/mesa/drivers/dri/nouveau/nouveau_shader.c index f911347d624..cdb79fca1e6 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_shader.c @@ -179,7 +179,7 @@ nvsBuildTextShader(GLcontext *ctx, GLenum target, const char *text) strlen(text), &nvs->mesa.vp); } else if (target == GL_FRAGMENT_PROGRAM_ARB) { - _mesa_init_fragment_program(ctx, &nvs->mesa.fp, GL_VERTEX_PROGRAM_ARB, 0); + _mesa_init_fragment_program(ctx, &nvs->mesa.fp, GL_FRAGMENT_PROGRAM_ARB, 0); _mesa_parse_arb_fragment_program(ctx, GL_FRAGMENT_PROGRAM_ARB, text, diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.h b/src/mesa/drivers/dri/nouveau/nouveau_shader.h index 8b4be9dfe7c..7329ccd9ead 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_shader.h @@ -194,6 +194,16 @@ typedef enum { NVS_TEX_TARGET_UNKNOWN = 0 } nvsTexTarget; +typedef enum { + NVS_SCALE_1X = 0, + NVS_SCALE_2X = 1, + NVS_SCALE_4X = 2, + NVS_SCALE_8X = 3, + NVS_SCALE_INV_2X = 5, + NVS_SCALE_INV_4X = 6, + NVS_SCALE_INV_8X = 7, +} nvsScale; + /* Arith/TEX instructions */ typedef struct nvs_instruction { nvsFragmentHeader header; @@ -203,6 +213,7 @@ typedef struct nvs_instruction { nvsRegister dest; unsigned int mask; + nvsScale dest_scale; nvsRegister src[3]; @@ -307,6 +318,7 @@ struct _nvsFunc { void (*InitInstruction) (nvsFunc *); int (*SupportsOpcode) (nvsFunc *, nvsOpcode); + int (*SupportsResultScale) (nvsFunc *, nvsScale); void (*SetOpcode) (nvsFunc *, unsigned int opcode, int slot); void (*SetCCUpdate) (nvsFunc *); @@ -314,6 +326,7 @@ struct _nvsFunc { nvsSwzComp *swizzle); void (*SetResult) (nvsFunc *, nvsRegister *, unsigned int mask, int slot); + void (*SetResultScale) (nvsFunc *, nvsScale); void (*SetSource) (nvsFunc *, nvsRegister *, int pos); void (*SetTexImageUnit) (nvsFunc *, int unit); void (*SetSaturate) (nvsFunc *); diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c index 28c6ad803b1..3bcc2ba755c 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c @@ -402,6 +402,7 @@ pass0_emit(nouveauShader *nvs, nvsFragmentHeader *parent, int fpos, sif->saturate = saturate; sif->dest = dst; sif->mask = mask; + sif->dest_scale = NVS_SCALE_1X; sif->src[0] = src0; sif->src[1] = src1; sif->src[2] = src2; @@ -667,25 +668,13 @@ pass0_emulate_instruction(nouveauShader *nvs, } break; case OPCODE_RSQ: - if (rec->const_half.file != NVS_FILE_CONST) { - GLfloat const_half[4] = { 0.5, 0.0, 0.0, 0.0 }; - pass0_make_reg(nvs, &rec->const_half, NVS_FILE_CONST, - _mesa_add_unnamed_constant( - nvs->mesa.vp.Base.Parameters, - const_half, 4)); - COPY_4V(nvs->params[rec->const_half.index].val, - const_half); - } pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); ARITHu(NVS_OP_LG2, temp, SMASK_X, 0, nvsAbs(nvsSwizzle(src[0], X, X, X, X)), nvr_unused, nvr_unused); - ARITHu(NVS_OP_MUL, temp, SMASK_X, 0, - nvsSwizzle(temp, X, X, X, X), - nvsNegate(rec->const_half), - nvr_unused); + nvsinst->dest_scale = NVS_SCALE_INV_2X; ARITH (NVS_OP_EX2, dest, mask, sat, - nvsSwizzle(temp, X, X, X, X), + nvsNegate(nvsSwizzle(temp, X, X, X, X)), nvr_unused, nvr_unused); break; case OPCODE_SCS: diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c index c106fd2d949..b043f877e42 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c @@ -135,6 +135,10 @@ pass2_add_instruction(nvsPtr nvs, nvsInstruction *inst, reg = pass2_mangle_reg(nvs, inst, inst->dest); shader->SetResult(shader, ®, inst->mask, slot); + + if (inst->dest_scale != NVS_SCALE_1X) { + shader->SetResultScale(shader, inst->dest_scale); + } } static int diff --git a/src/mesa/drivers/dri/nouveau/nouveau_sync.c b/src/mesa/drivers/dri/nouveau/nouveau_sync.c index 0bf20e723bb..e7bc4fcd5ee 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_sync.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_sync.c @@ -14,6 +14,10 @@ nouveau_notifier_new(GLcontext *ctx, GLuint handle) nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); nouveau_notifier *notifier; +#ifdef NOUVEAU_RING_DEBUG + return NULL; +#endif + notifier = CALLOC_STRUCT(nouveau_notifier_t); if (!notifier) return NULL; @@ -53,6 +57,10 @@ nouveau_notifier_reset(nouveau_notifier *notifier) { volatile GLuint *n = notifier->mem->map; +#ifdef NOUVEAU_RING_DEBUG + return; +#endif + n[NV_NOTIFY_TIME_0 /4] = 0x00000000; n[NV_NOTIFY_TIME_1 /4] = 0x00000000; n[NV_NOTIFY_RETURN_VALUE/4] = 0x00000000; @@ -67,6 +75,10 @@ nouveau_notifier_wait_status(nouveau_notifier *notifier, GLuint status, volatile GLuint *n = notifier->mem->map; unsigned int time = 0; +#ifdef NOUVEAU_RING_DEBUG + return GL_TRUE; +#endif + while (time <= timeout) { if (n[NV_NOTIFY_STATE/4] & NV_NOTIFY_STATE_ERROR_CODE_MASK) { MESSAGE("Notifier returned error: 0x%04x\n", @@ -114,6 +126,10 @@ GLboolean nouveauSyncInitFuncs(GLcontext *ctx) { nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); +#ifdef NOUVEAU_RING_DEBUG + return GL_TRUE; +#endif + nmesa->syncNotifier = nouveau_notifier_new(ctx, NvSyncNotify); if (!nmesa->syncNotifier) { MESSAGE("Failed to create channel sync notifier\n"); diff --git a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c b/src/mesa/drivers/dri/nouveau/nv40_fragprog.c index 8bca6ae9383..3e4ae0496e4 100644 --- a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c +++ b/src/mesa/drivers/dri/nouveau/nv40_fragprog.c @@ -11,6 +11,30 @@ struct _op_xlat NVFP_TX_BOP[64]; * - These extend the NV30 routines, which are almost identical. NV40 * just has branching hacked into the instruction set. */ +static int +NV40FPSupportsResultScale(nvsFunc *shader, nvsScale scale) +{ + switch (scale) { + case NVS_SCALE_1X: + case NVS_SCALE_2X: + case NVS_SCALE_4X: + case NVS_SCALE_8X: + case NVS_SCALE_INV_2X: + case NVS_SCALE_INV_4X: + case NVS_SCALE_INV_8X: + return 1; + default: + return 0; + } +} + +static void +NV40FPSetResultScale(nvsFunc *shader, nvsScale scale) +{ + shader->inst[2] &= ~NV40_FP_OP_DST_SCALE_MASK; + shader->inst[2] |= ((unsigned int)scale << NV40_FP_OP_DST_SCALE_SHIFT); +} + static void NV40FPSetBranchTarget(nvsFunc *shader, int addr) { @@ -179,6 +203,9 @@ NV40FPInitShaderFuncs(nvsFunc * shader) MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_REP , NVS_OP_REP , -1, -1, -1); MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_RET , NVS_OP_RET , -1, -1, -1); + shader->SupportsResultScale = NV40FPSupportsResultScale; + shader->SetResultScale = NV40FPSetResultScale; + /* fragment.facing */ shader->GetSourceID = NV40FPGetSourceID; diff --git a/src/mesa/drivers/dri/nouveau/nv40_shader.h b/src/mesa/drivers/dri/nouveau/nv40_shader.h index 2a2b5639b6c..584f4c23e08 100644 --- a/src/mesa/drivers/dri/nouveau/nv40_shader.h +++ b/src/mesa/drivers/dri/nouveau/nv40_shader.h @@ -399,8 +399,8 @@ /* high order bits of SRC1 */ #define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31) -#define NV40_FP_OP_SRC_SCALE_SHIFT 28 -#define NV40_FP_OP_SRC_SCALE_MASK (3 << 28) +#define NV40_FP_OP_DST_SCALE_SHIFT 28 +#define NV40_FP_OP_DST_SCALE_MASK (3 << 28) /* SRC1 LOOP */ #define NV40_FP_OP_LOOP_INCR_SHIFT 19 |