diff options
| author | Francisco Jerez <[email protected]> | 2016-06-30 19:39:24 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-07-07 14:16:38 -0700 |
| commit | 04f74d66293222d5e1905cfb930bfa083e30463c (patch) | |
| tree | 1be8527c4f7def04546497fd77cc847bbe02296c /src/mesa/drivers/dri | |
| parent | 8fd5779da44cd6bf822a52339f3772581aa1e312 (diff) | |
i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
Shouldn't cause any functional changes at this point, but we have
forgotten to apply this workaround several times in the past, make
sure it doesn't happen again.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 21 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex.c | 8 |
4 files changed, 11 insertions, 35 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 690c2f65fd9..c3d341fd111 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -925,15 +925,6 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) const unsigned dc_flush = brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; - if (brw->gen == 6) { - /* Hardware workaround: SNB B-Spec says: - * - * Before a PIPE_CONTROL with Write Cache Flush Enable = 1, a - * PIPE_CONTROL with any non-zero post-sync-op is required. - */ - brw_emit_post_sync_nonzero_flush(brw); - } - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 4672efdffc3..586355d8c22 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -109,6 +109,17 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) OUT_BATCH(0); ADVANCE_BATCH(); } else if (brw->gen >= 6) { + if (brw->gen == 6 && + (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { + /* Hardware workaround: SNB B-Spec says: + * + * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush + * Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is + * required. + */ + brw_emit_post_sync_nonzero_flush(brw); + } + flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags); BEGIN_BATCH(5); @@ -325,16 +336,6 @@ brw_emit_mi_flush(struct brw_context *brw) PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL; - - if (brw->gen == 6) { - /* Hardware workaround: SNB B-Spec says: - * - * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache - * Flush Enable =1, a PIPE_CONTROL with any non-zero - * post-sync-op is required. - */ - brw_emit_post_sync_nonzero_flush(brw); - } } brw_emit_pipe_control_flush(brw, flags); } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 939f9a08c58..707a9d2af3d 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -1061,14 +1061,6 @@ brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo) return; if (brw->gen >= 6) { - if (brw->gen == 6) { - /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache - * Flush Enable = 1, a PIPE_CONTROL with any non-zero - * post-sync-op is required. - */ - brw_emit_post_sync_nonzero_flush(brw); - } - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index a802d5a9186..8c32fe395c4 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -364,14 +364,6 @@ intel_texture_barrier(struct gl_context *ctx) struct brw_context *brw = brw_context(ctx); if (brw->gen >= 6) { - if (brw->gen == 6) { - /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache - * Flush Enable = 1, a PIPE_CONTROL with any non-zero - * post-sync-op is required. - */ - brw_emit_post_sync_nonzero_flush(brw); - } - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | |