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authorDave Airlie <[email protected]>2009-02-09 23:19:42 +1000
committerDave Airlie <[email protected]>2009-02-09 23:19:42 +1000
commit9df844b109a9d2cc1d3b16315c34ef84f147c5b6 (patch)
tree087bc557524210411355813b696f5938a75bb568 /src/mesa/drivers/dri/radeon
parent3fafaf8959681cc41c988607bb6e387bab4fe1b5 (diff)
radeon: fix alignment issues in ELT code
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_ioctl.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 1a33595884e..0c363b39bde 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -251,7 +251,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
#if RADEON_OLD_PACKETS
- BEGIN_BATCH(6);
+ BEGIN_BATCH(8);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3);
OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_nr);
@@ -363,6 +363,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
GLuint min_nr )
{
GLushort *retval;
+ int align_min_nr;
BATCH_LOCALS(&rmesa->radeon);
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
@@ -373,8 +374,11 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
+ /* round up min_nr to align the state */
+ align_min_nr = (min_nr + 1) & ~1;
+
#if RADEON_OLD_PACKETS
- BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(min_nr)/4);
+ BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0);
OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(0xffff);
@@ -385,7 +389,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
#else
- BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(min_nr)/4);
+ BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0);
OUT_BATCH(vertex_format);
OUT_BATCH(primitive |