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authorEric Anholt <[email protected]>2013-03-14 14:41:37 -0700
committerEric Anholt <[email protected]>2013-04-01 16:17:25 -0700
commit740350c982bd2735b9eb9063c2b91856b6f1ad31 (patch)
tree4304356b9eefd81c2ab17382a022fb2290cea684 /src/mesa/drivers/dri/intel
parent2f41a601455e6e0366e28b6b84871842cb4bd341 (diff)
i965: Make the fragment shader pull constants index by dwords, not vec4s.
We want to load vec4s, since loading a vec4 instead of a dword is basically no increased latency. But for variable indexed access, the previous requirement of aligned vec4s for a sampler LD was hard to implement. Note that this change only affects those messages that use the surface format, like sampler LDs, but not to the untyped data cache loads we've used in other cases. No significant performance difference on my GLSL demo with uniforms forced to take the varying pull constants path (n=4). NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/intel')
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 958db1cade1..b130c02e6be 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -203,13 +203,14 @@ struct intel_context
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
- uint32_t *out_offset);
+ uint32_t *out_offset,
+ bool dword_pitch);
/** \} */
} vtbl;
GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */
GLuint NewGLState;
-
+
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;