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authorDave Airlie <[email protected]>2009-06-07 16:51:32 +1000
committerDave Airlie <[email protected]>2009-06-07 16:51:32 +1000
commit545e574cd9a2a659cd9a93879dff8884bd247558 (patch)
treef56d65eaa851edfb1248a6fc8ac0bae4cc98eff5 /src/mesa/drivers/dri/intel/intel_tex_layout.c
parente2aedfa62079ff1a333e1f4e56faea303cc36edb (diff)
parentf1edfa09ea50e8833ddbf241da4d36fd38685e9d (diff)
Merge remote branch 'origin/master' into radeon-rewrite
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_tex_layout.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index e6f9a417790..b8be7ef41a2 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -52,7 +52,9 @@ GLuint intel_compressed_alignment(GLenum internalFormat)
return alignment;
}
-void i945_miptree_layout_2d( struct intel_context *intel, struct intel_mipmap_tree *mt )
+void i945_miptree_layout_2d( struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ uint32_t tiling )
{
GLint align_h = 2, align_w = 4;
GLuint level;
@@ -86,13 +88,18 @@ void i945_miptree_layout_2d( struct intel_context *intel, struct intel_mipmap_tr
if (mip1_width > mt->pitch) {
mt->pitch = mip1_width;
+
+ if (tiling == I915_TILING_X)
+ mt->pitch = ALIGN(mt->pitch * mt->cpp, 512) / mt->cpp;
+ if (tiling == I915_TILING_Y)
+ mt->pitch = ALIGN(mt->pitch * mt->cpp, 128) / mt->cpp;
}
}
/* Pitch must be a whole number of dwords, even though we
* express it in texels.
*/
- mt->pitch = intel_miptree_pitch_align (intel, mt, mt->pitch);
+ mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->pitch);
mt->total_height = 0;
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {