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authorPaul Berry <[email protected]>2013-03-21 09:11:12 -0700
committerPaul Berry <[email protected]>2013-08-23 11:03:12 -0700
commiteaa63cbbc2f5ae415fc89ef6fd74c5b26ad622fd (patch)
tree87b2422e2775a9cff480521620c81ea0f8a9901b /src/mesa/drivers/dri/i965
parenta9e8c10bd76f9a94b878b76bb5ae696beeaae2e0 (diff)
i965/gs: Add a flag allowing URB write messages to use a per-slot offset.
This will be used by geometry shaders to implement the EmitVertex() function, since it requires writing data to a dynamically-determined offset within the geometry shader's URB entry. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h6
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c4
2 files changed, 8 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index ae4cab56637..9053ea2f86b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -252,6 +252,12 @@ enum brw_urb_write_flags {
BRW_URB_WRITE_COMPLETE = 0x8,
/**
+ * Indicates that an additional offset (which may be different for the two
+ * vec4 slots) is stored in the message header (gen == 7).
+ */
+ BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
+
+ /**
* Convenient combination of flags: end the thread while simultaneously
* marking the given URB entry as complete.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 622b22f7981..b55b57e2e82 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -531,8 +531,8 @@ static void brw_set_urb_message( struct brw_compile *p,
insn->bits3.urb_gen7.offset = offset;
assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
insn->bits3.urb_gen7.swizzle_control = swizzle_control;
- /* per_slot_offset = 0 makes it ignore offsets in message header */
- insn->bits3.urb_gen7.per_slot_offset = 0;
+ insn->bits3.urb_gen7.per_slot_offset =
+ flags & BRW_URB_WRITE_PER_SLOT_OFFSET ? 1 : 0;
insn->bits3.urb_gen7.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
} else if (brw->gen >= 5) {
insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */