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authorKenneth Graunke <[email protected]>2013-05-16 19:25:14 -0700
committerKenneth Graunke <[email protected]>2013-05-20 13:03:18 -0700
commitd1e4e9960cbdfce6078cdc377809ea76c2eb7078 (patch)
tree4ffcfe498c3fdaf3f33f06aac166960cc80a12e5 /src/mesa/drivers/dri/i965
parent5ebe9523f970991ef67e58392040e3fc996aada7 (diff)
i965: Handle rasterizer discard in the clipper rather than SOL on Gen7.
In order to implement the GL_PRIMITIVES_GENERATED query in a sane fashion on our hardware, we can't discard primitives until the clipper. The patch after next explains the rationale. By setting the clipper to REJECT_ALL mode, all primitives get thrown away, so rendering is still appropriately disabled. This may negatively impact performance in the rasterizer discard case, but it's unclear how much and this hasn't been observed to be a bottleneck in any application we've looked at. The clipper is the very next stage in the pipeline, so I don't think it will be terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_clip_state.c11
-rw-r--r--src/mesa/drivers/dri/i965/gen7_sol_state.c7
2 files changed, 11 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_clip_state.c b/src/mesa/drivers/dri/i965/gen7_clip_state.c
index 7c9f6c1a4c8..aae78953a81 100644
--- a/src/mesa/drivers/dri/i965/gen7_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_clip_state.c
@@ -102,6 +102,13 @@ upload_clip_state(struct brw_context *brw)
dw2 |= GEN6_CLIP_GB_TEST;
}
+ /* BRW_NEW_RASTERIZER_DISCARD */
+ if (ctx->RasterDiscard) {
+ dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
+ perf_debug("Rasterizer discard is currently implemented via the clipper; "
+ "using the SOL unit may be faster.");
+ }
+
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
OUT_BATCH(dw1);
@@ -122,7 +129,9 @@ const struct brw_tracked_state gen7_clip_state = {
_NEW_POLYGON |
_NEW_LIGHT |
_NEW_TRANSFORM),
- .brw = BRW_NEW_CONTEXT | BRW_NEW_META_IN_PROGRESS,
+ .brw = BRW_NEW_CONTEXT |
+ BRW_NEW_META_IN_PROGRESS |
+ BRW_NEW_RASTERIZER_DISCARD,
.cache = CACHE_NEW_WM_PROG
},
.emit = upload_clip_state,
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index f5703362968..1e484dc1bcf 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -195,10 +195,6 @@ upload_3dstate_streamout(struct brw_context *brw, bool active,
uint32_t dw1 = 0, dw2 = 0;
int i;
- /* BRW_NEW_RASTERIZER_DISCARD */
- if (ctx->RasterDiscard)
- dw1 |= SO_RENDERING_DISABLE;
-
if (active) {
int urb_entry_read_offset = 0;
int urb_entry_read_length = (vue_map->num_slots + 1) / 2 -
@@ -267,8 +263,7 @@ const struct brw_tracked_state gen7_sol_state = {
.brw = (BRW_NEW_BATCH |
BRW_NEW_VERTEX_PROGRAM |
BRW_NEW_VUE_MAP_GEOM_OUT |
- BRW_NEW_TRANSFORM_FEEDBACK |
- BRW_NEW_RASTERIZER_DISCARD)
+ BRW_NEW_TRANSFORM_FEEDBACK)
},
.emit = upload_sol_state,
};