Merge branch 'master' into i915-superioctl

19 files changed, 84 insertions, 181 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index ae46d7a86e0..ba2f0edf513 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -43,7 +43,8 @@ static void upload_clip_unit( struct brw_context *brw )
    memset(&clip, 0, sizeof(clip));
 
    /* CACHE_NEW_CLIP_PROG */
-   clip.thread0.grf_reg_count = ((brw->clip.prog_data->total_grf-1) & ~15) / 16;
+   clip.thread0.grf_reg_count =
+      ALIGN(brw->clip.prog_data->total_grf, 16) / 16 - 1;
    clip.thread0.kernel_start_pointer = brw->clip.prog_gs_offset >> 6;
    clip.thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
    clip.thread3.const_urb_entry_read_length = brw->clip.prog_data->curb_read_length;
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index d3c88c1dca0..fa4ea42aa6e 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -304,7 +304,7 @@ static void upload_constant_buffer(struct brw_context *brw)
       
       if (!brw_pool_alloc(pool, 
 			  bufsz,
-			  6,
+			  1 << 6,
 			  &brw->curbe.gs_offset)) {
 	 _mesa_printf("out of GS memory for curbe\n");
 	 assert(0);
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index fc2e3035af1..b7795703fd3 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -290,7 +290,7 @@ static void get_space( struct brw_context *brw,
 		       struct gl_buffer_object **vbo_return,
 		       GLuint *offset_return )
 {
-   size = (size + 63) & ~63;
+   size = ALIGN(size, 64);
    
    if (brw->vb.upload.offset + size > BRW_UPLOAD_INIT_SIZE)
       wrap_buffers(brw, size);
@@ -541,7 +541,8 @@ GLboolean brw_upload_vertices( struct brw_context *brw,
    
    for (i = 0; i < nr_enabled; i++) {
       OUT_BATCH( vbp.vb[i].vb0.dword );
-      OUT_BATCH( bmBufferOffset(&brw->intel, vbp.vb[i].buffer) + vbp.vb[i].offset);
+      OUT_RELOC( vbp.vb[i].buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+		 vbp.vb[i].offset);
       OUT_BATCH( vbp.vb[i].max_index );
       OUT_BATCH( vbp.vb[i].instance_data_step_rate );
    }
@@ -632,8 +633,9 @@ void brw_upload_indices( struct brw_context *brw,
 
       BEGIN_BATCH(4, 0);
       OUT_BATCH( ib.header.dword );
-      OUT_BATCH( bmBufferOffset(intel, buffer) + offset );
-      OUT_BATCH( bmBufferOffset(intel, buffer) + offset + ib_size );
+      OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset);
+      OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+		 offset + ib_size);
       OUT_BATCH( 0 );
       ADVANCE_BATCH();
    }
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 5826c01d4f9..5db4dd4603b 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -46,7 +46,8 @@ static void upload_gs_unit( struct brw_context *brw )
 
    /* CACHE_NEW_GS_PROG */
    if (brw->gs.prog_active) {
-      gs.thread0.grf_reg_count = ((brw->gs.prog_data->total_grf-1) & ~15) / 16;
+      gs.thread0.grf_reg_count =
+	 ALIGN(brw->gs.prog_data->total_grf, 16) / 16 - 1;
       gs.thread0.kernel_start_pointer = brw->gs.prog_gs_offset >> 6;
       gs.thread3.urb_entry_read_length = brw->gs.prog_data->urb_read_length;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 236c6fd42a5..2257916aaec 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -118,7 +118,7 @@ static void upload_sf_unit( struct brw_context *brw )
    memset(&sf, 0, sizeof(sf));
 
    /* CACHE_NEW_SF_PROG */
-   sf.thread0.grf_reg_count = ((brw->sf.prog_data->total_grf-1) & ~15) / 16;
+   sf.thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
    sf.thread0.kernel_start_pointer = brw->sf.prog_gs_offset >> 6;
    sf.thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 98d765ac0e0..0e73ff8390f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -148,7 +148,7 @@ GLuint brw_upload_cache( struct brw_cache *cache,
    GLuint hash = hash_key(key, key_size);
    void *tmp = _mesa_malloc(key_size + cache->aux_size);
    
-   if (!brw_pool_alloc(cache->pool, data_size, 6, &offset)) {
+   if (!brw_pool_alloc(cache->pool, data_size, 1 << 6, &offset)) {
       /* Should not be possible: 
        */
       _mesa_printf("brw_pool_alloc failed\n");
diff --git a/src/mesa/drivers/dri/i965/brw_state_pool.c b/src/mesa/drivers/dri/i965/brw_state_pool.c
index 708ae857ab5..eda92a2fa89 100644
--- a/src/mesa/drivers/dri/i965/brw_state_pool.c
+++ b/src/mesa/drivers/dri/i965/brw_state_pool.c
@@ -41,10 +41,9 @@ GLboolean brw_pool_alloc( struct brw_mem_pool *pool,
 			  GLuint align,
 			  GLuint *offset_return)
 {
-   GLuint align_mask = (1<<align)-1;
-   GLuint fixup = ((pool->offset + align_mask) & ~align_mask) - pool->offset;
+   GLuint fixup = ALIGN(pool->offset, align) - pool->offset;
 
-   size = (size + 3) & ~3;
+   size = ALIGN(size, 4);
 
    if (pool->offset + fixup + size >= pool->size) {
       _mesa_printf("%s failed\n", __FUNCTION__);
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 2094a1c8ad7..e306c9cf106 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -37,8 +37,6 @@
 #include "intel_tex_layout.h"
 #include "macros.h"
 
-#define ALIGN(value, alignment)  ((value + alignment - 1) & ~(alignment - 1))
-
 GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 {
    /* XXX: these vary depending on image format: 
@@ -64,7 +62,7 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
           mt->pitch = ALIGN(width, align_w);
           pack_y_pitch = (height + 3) / 4;
       } else {
-          mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp;
+          mt->pitch = ALIGN(mt->width0 * mt->cpp, 4) / mt->cpp;
           pack_y_pitch = ALIGN(mt->height0, align_h);
       }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index c225bf8f5c5..f561979138c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -44,7 +44,7 @@ static void upload_vs_unit( struct brw_context *brw )
 
    /* CACHE_NEW_VS_PROG */
    vs.thread0.kernel_start_pointer = brw->vs.prog_gs_offset >> 6;
-   vs.thread0.grf_reg_count = ((brw->vs.prog_data->total_grf-1) & ~15) / 16;
+   vs.thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
    vs.thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
    vs.thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
    vs.thread3.dispatch_grf_start_reg = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 5b4f2abd0e2..351de6d90ef 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -62,7 +62,7 @@ static void upload_wm_unit(struct brw_context *brw )
    memset(&wm, 0, sizeof(wm));
 
    /* CACHE_NEW_WM_PROG */
-   wm.thread0.grf_reg_count = ((brw->wm.prog_data->total_grf-1) & ~15) / 16;
+   wm.thread0.grf_reg_count = ALIGN(brw->wm.prog_data->total_grf, 16) / 16 - 1;
    wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6;
    wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
    wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
@@ -71,7 +71,7 @@ static void upload_wm_unit(struct brw_context *brw )
    wm.wm5.max_threads = max_threads;      
 
    if (brw->wm.prog_data->total_scratch) {
-      GLuint per_thread = (brw->wm.prog_data->total_scratch + 1023) / 1024;
+      GLuint per_thread = ALIGN(brw->wm.prog_data->total_scratch, 1024);
       GLuint total = per_thread * (max_threads + 1);
 
       /* Scratch space -- just have to make sure there is sufficient
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index a85121122fc..65760c40d47 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -168,7 +168,7 @@ static GLboolean alloc_from_pool( struct intel_context *intel,
    if (!block)
       return GL_FALSE;
 
-   sz = (buf->size + align-1) & ~(align-1);
+   sz = ALIGN(buf->size, align);
 
    block->mem = mmAllocMem(pool->heap, 
 			   sz, 
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index fb58c0e708c..7a6293b5578 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -37,7 +37,7 @@ static void intel_batchbuffer_reset( struct intel_batchbuffer *batch )
    assert(batch->map == NULL);
 
    batch->offset = (unsigned long)batch->ptr;
-   batch->offset = (batch->offset + 63) & ~63;
+   batch->offset = ALIGN(batch->offset, 64);
    batch->ptr = (unsigned char *) batch->offset;
 
    if (BATCH_SZ - batch->offset < BATCH_REFILL) {
@@ -208,7 +208,7 @@ void intel_batchbuffer_align( struct intel_batchbuffer *batch,
 			      GLuint sz )
 {
    unsigned long ptr = (unsigned long) batch->ptr;
-   unsigned long aptr = (ptr + align) & ~((unsigned long)align-1);
+   unsigned long aptr = ALIGN(ptr, align);
    GLuint fixup = aptr - ptr;
 
    if (intel_batchbuffer_space(batch) < fixup + sz)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 25e0a65e99f..c40cad96383 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -121,6 +121,12 @@ void intel_batchbuffer_align( struct intel_batchbuffer *batch,
 #define BATCH_LOCALS 
 #define BEGIN_BATCH(n, flags) intel_batchbuffer_require_space(intel->batch, n*4, flags)
 #define OUT_BATCH(d)  intel_batchbuffer_emit_dword(intel->batch, d)
+
+#define OUT_RELOC(buf, flags, delta) do { 				\
+   assert((delta) >= 0);						\
+   OUT_BATCH(bmBufferOffset(intel, buf) + delta);				\
+} while (0)
+
 #define ADVANCE_BATCH() do { } while(0)
 
 
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index f88cbb2328d..d1c1c8afb6a 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -110,8 +110,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
       } 
       else {
 	 BR13 = (0xCC << 16) | (1<<24) | (1<<25);
-	 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
-		XY_SRC_COPY_BLT_WRITE_RGB);
+	 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
       }
 
       if (src->tiled) {
@@ -145,10 +144,10 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
 	 OUT_BATCH( dst_pitch | BR13 );
 	 OUT_BATCH( (tmp.y1 << 16) | tmp.x1 );
 	 OUT_BATCH( (tmp.y2 << 16) | tmp.x2 );
-	 OUT_BATCH( bmBufferOffset(intel, dst->buffer) );
+	 OUT_RELOC( dst->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, 0 );
 	 OUT_BATCH( (tmp.y1 << 16) | tmp.x1 );
 	 OUT_BATCH( src_pitch );
-	 OUT_BATCH( bmBufferOffset(intel, src->buffer) ); 
+	 OUT_RELOC( src->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0 );
 	 ADVANCE_BATCH();
       }
    }
@@ -199,8 +198,7 @@ void intelEmitFillBlit( struct intel_context *intel,
       break;
    case 4:
       BR13 = (0xF0 << 16) | (1<<24) | (1<<25);
-      CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
-	     XY_COLOR_BLT_WRITE_RGB);
+      CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
       break;
    default:
       return;
@@ -216,7 +214,7 @@ void intelEmitFillBlit( struct intel_context *intel,
    OUT_BATCH( dst_pitch | BR13 );
    OUT_BATCH( (y << 16) | x );
    OUT_BATCH( ((y+h) << 16) | (x+w) );
-   OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset );
+   OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset );
    OUT_BATCH( color );
    ADVANCE_BATCH();
 }
@@ -290,8 +288,7 @@ void intelEmitCopyBlit( struct intel_context *intel,
    case 4:
       BR13 = (translate_raster_op(logic_op) << 16) | (1<<24) |
 	  (1<<25);
-      CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
-	     XY_SRC_COPY_BLT_WRITE_RGB);
+      CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
       break;
    default:
       return;
@@ -328,10 +325,12 @@ void intelEmitCopyBlit( struct intel_context *intel,
       OUT_BATCH( dst_pitch | BR13 );
       OUT_BATCH( (dst_y << 16) | dst_x );
       OUT_BATCH( (dst_y2 << 16) | dst_x2 );
-      OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset );	
+      OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+		 dst_offset );
       OUT_BATCH( (src_y << 16) | src_x );
       OUT_BATCH( src_pitch );
-      OUT_BATCH( bmBufferOffset(intel, src_buffer) + src_offset ); 
+      OUT_RELOC( src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+		 src_offset );
       ADVANCE_BATCH();
    }
    else {
@@ -340,10 +339,11 @@ void intelEmitCopyBlit( struct intel_context *intel,
       OUT_BATCH( (dst_pitch & 0xffff) | BR13 );
       OUT_BATCH( (0 << 16) | dst_x );
       OUT_BATCH( (h << 16) | dst_x2 );
-      OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset + dst_y * dst_pitch );	
-      OUT_BATCH( (0 << 16) | src_x );
+      OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+		 dst_offset + dst_y * dst_pitch );
       OUT_BATCH( (src_pitch & 0xffff) );
-      OUT_BATCH( bmBufferOffset(intel, src_buffer) + src_offset + src_y * src_pitch ); 
+      OUT_RELOC( src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+		 src_offset + src_y * src_pitch );
       ADVANCE_BATCH();
    }
 }
@@ -388,12 +388,11 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags)
       break;
    case 4:
       BR13 = (0xF0 << 16) | (1<<24) | (1<<25);
-      BACK_CMD = FRONT_CMD = (XY_COLOR_BLT_CMD |
-			      XY_COLOR_BLT_WRITE_ALPHA | 
-			      XY_COLOR_BLT_WRITE_RGB);
+      BACK_CMD = FRONT_CMD = XY_COLOR_BLT_CMD |
+	 XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
       DEPTH_CMD = XY_COLOR_BLT_CMD;
-      if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_COLOR_BLT_WRITE_RGB;
-      if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
+      if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_BLT_WRITE_RGB;
+      if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_BLT_WRITE_ALPHA;
       break;
    default:
       return;
@@ -484,7 +483,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags)
 	    OUT_BATCH( front_pitch | BR13 );
 	    OUT_BATCH( (b.y1 << 16) | b.x1 );
 	    OUT_BATCH( (b.y2 << 16) | b.x2 );
-	    OUT_BATCH( bmBufferOffset(intel, front->buffer) );
+	    OUT_RELOC( front->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+		       0 );
 	    OUT_BATCH( clear_color );
 	    ADVANCE_BATCH();
 	 }
@@ -495,7 +495,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags)
 	    OUT_BATCH( back_pitch | BR13 );
 	    OUT_BATCH( (b.y1 << 16) | b.x1 );
 	    OUT_BATCH( (b.y2 << 16) | b.x2 );
-	    OUT_BATCH( bmBufferOffset(intel, back->buffer) );
+	    OUT_RELOC( back->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+		       0 );
 	    OUT_BATCH( clear_color );
 	    ADVANCE_BATCH();
 	 }
@@ -506,7 +507,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags)
 	    OUT_BATCH( depth_pitch | BR13 );
 	    OUT_BATCH( (b.y1 << 16) | b.x1 );
 	    OUT_BATCH( (b.y2 << 16) | b.x2 );
-	    OUT_BATCH( bmBufferOffset(intel, depth->buffer) );
+	    OUT_RELOC( depth->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+		       0 );
 	    OUT_BATCH( clear_depth );
 	    ADVANCE_BATCH();
 	 }      
@@ -517,11 +519,6 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags)
 }
 
 
-
-#define BR13_565  0x1
-#define BR13_8888 0x3
-
-
 void
 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 				  GLuint cpp,
@@ -535,9 +532,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 				  GLshort w, GLshort h,
 				  GLenum logic_op)
 {
-   struct xy_setup_blit setup;
    struct xy_text_immediate_blit text;
-   int dwords = ((src_size + 7) & ~7) / 4;
+   int dwords = ALIGN(src_size, 8) / 4;
+   uint32_t opcode, br13;
 
    assert( logic_op - GL_CLEAR >= 0 );
    assert( logic_op - GL_CLEAR < 0x10 );
@@ -554,31 +551,6 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
        __FUNCTION__,
        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 
-   memset(&setup, 0, sizeof(setup));
-   
-   setup.br0.client = CLIENT_2D;
-   setup.br0.opcode = OPCODE_XY_SETUP_BLT;
-   setup.br0.write_alpha = (cpp == 4);
-   setup.br0.write_rgb = (cpp == 4);
-   setup.br0.dst_tiled = dst_tiled;
-   setup.br0.length = (sizeof(setup) / sizeof(int)) - 2;
-      
-   setup.br13.dest_pitch = dst_pitch;
-   setup.br13.rop = translate_raster_op(logic_op);
-   setup.br13.color_depth = (cpp == 4) ? BR13_8888 : BR13_565;
-   setup.br13.clipping_enable = 0;
-   setup.br13.mono_source_transparency = 1;
-
-   setup.dw2.clip_y1 = 0;
-   setup.dw2.clip_x1 = 0;
-   setup.dw3.clip_y2 = 100;
-   setup.dw3.clip_x2 = 100;
-
-   setup.dest_base_addr = bmBufferOffset(intel, dst_buffer) + dst_offset;
-   setup.background_color = 0;
-   setup.foreground_color = fg_color;
-   setup.pattern_base_addr = 0;
-
    memset(&text, 0, sizeof(text));
    text.dw0.client = CLIENT_2D;
    text.dw0.opcode = OPCODE_XY_TEXT_IMMEDIATE_BLT;
@@ -594,15 +566,33 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    text.dw2.dest_x2 = x + w;
 
    intel_batchbuffer_require_space( intel->batch,
-				    sizeof(setup) + 
+				    (8 * 4) +
 				    sizeof(text) + 
 				    dwords,
 				    INTEL_BATCH_NO_CLIPRECTS );
 
-   intel_batchbuffer_data( intel->batch,
-			   &setup,
-			   sizeof(setup),
-			   INTEL_BATCH_NO_CLIPRECTS );
+   opcode = XY_SETUP_BLT_CMD;
+   if (cpp == 4)
+      opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
+   if (dst_tiled)
+      opcode |= XY_DST_TILED;
+
+   br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
+   if (cpp == 2)
+      br13 |= BR13_565;
+   else
+      br13 |= BR13_8888;
+
+   BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS);
+   OUT_BATCH(opcode);
+   OUT_BATCH(br13);
+   OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
+   OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
+   OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
+   OUT_BATCH(0); /* bg */
+   OUT_BATCH(fg_color); /* fg */
+   OUT_BATCH(0); /* pattern base addr */
+   ADVANCE_BATCH();
 
    intel_batchbuffer_data( intel->batch,
 			   &text,
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 2cf311c7135..7ec316aa8ae 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -498,7 +498,7 @@ GLboolean intelInitContext( struct intel_context *intel,
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
    }
-   else if (driQueryOptionb (&intelScreen->optionCache, "force_s3tc_enable")) {
+   else if (driQueryOptionb (&intel->optionCache, "force_s3tc_enable")) {
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index f63c2f613dc..65898caaa75 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -252,6 +252,8 @@ void UNLOCK_HARDWARE( struct intel_context *intel );
 #define SUBPIXEL_X 0.125
 #define SUBPIXEL_Y 0.125
 
+#define ALIGN(value, alignment)  ((value + alignment - 1) & ~(alignment - 1))
+
 /* ================================================================
  * Color packing:
  */
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0fb33e27f47..268a982a97f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -233,8 +233,8 @@ GLboolean intel_miptree_image_data(struct intel_context *intel,
 
    if (dst->compressed) {
        alignment = intel_compressed_alignment(dst->internal_format);
-       src_row_pitch = ((src_row_pitch + alignment - 1) & ~(alignment - 1));
-       width = ((width + alignment - 1) & ~(alignment - 1));
+       src_row_pitch = ALIGN(src_row_pitch, alignment);
+       width = ALIGN(width, alignment);
        height = (height + 3) / 4;
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 79c1fee9c07..3777422619b 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -91,11 +91,6 @@ static void set_bit( GLubyte *dest,
    dest[bit/8] |= 1 << (bit % 8);
 }
 
-static int align(int x, int align)
-{
-   return (x + align - 1) & ~(align - 1);
-}
-
 /* Extract a rectangle's worth of data from the bitmap.  Called
  * per-cliprect.
  */
@@ -147,7 +142,7 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height,
       }
 
       if (row_align)
-	 bit = (bit + row_align - 1) & ~(row_align - 1);
+	 bit = ALIGN(bit, row_align);
    }
 
    return count;
@@ -268,7 +263,7 @@ do_blit_bitmap( GLcontext *ctx,
 	    for (px = 0; px < box_w; px += DX) { 
 	       int h = MIN2(DY, box_h - py);
 	       int w = MIN2(DX, box_w - px); 
-	       GLuint sz = align(align(w,8) * h, 64)/8;
+	       GLuint sz = ALIGN(ALIGN(w,8) * h, 64)/8;
 	       GLenum logic_op = ctx->Color.ColorLogicOpEnabled ?
 		  ctx->Color.LogicOp : GL_COPY;
 
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
deleted file mode 100644
index 3c448b3559a..00000000000
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**************************************************************************
- * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- * 
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- * 
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
- **************************************************************************/
-
-
-#ifndef _INTEL_REG_H_
-#define _INTEL_REG_H_
-
-
-
-#define CMD_3D (0x3<<29)
-
-
-#define _3DPRIMITIVE         ((0x3<<29)|(0x1f<<24))
-#define PRIM_INDIRECT            (1<<23)
-#define PRIM_INLINE              (0<<23)
-#define PRIM_INDIRECT_SEQUENTIAL (0<<17)
-#define PRIM_INDIRECT_ELTS       (1<<17)
-
-#define PRIM3D_TRILIST		(0x0<<18)
-#define PRIM3D_TRISTRIP 	(0x1<<18)
-#define PRIM3D_TRISTRIP_RVRSE	(0x2<<18)
-#define PRIM3D_TRIFAN		(0x3<<18)
-#define PRIM3D_POLY		(0x4<<18)
-#define PRIM3D_LINELIST 	(0x5<<18)
-#define PRIM3D_LINESTRIP	(0x6<<18)
-#define PRIM3D_RECTLIST 	(0x7<<18)
-#define PRIM3D_POINTLIST	(0x8<<18)
-#define PRIM3D_DIB		(0x9<<18)
-#define PRIM3D_MASK		(0x1f<<18)
-
-#define I915PACKCOLOR4444(r,g,b,a) \
-  ((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4))
-
-#define I915PACKCOLOR1555(r,g,b,a) \
-  ((((r) & 0xf8) << 7) | (((g) & 0xf8) << 2) | (((b) & 0xf8) >> 3) | \
-    ((a) ? 0x8000 : 0))
-
-#define I915PACKCOLOR565(r,g,b) \
-  ((((r) & 0xf8) << 8) | (((g) & 0xfc) << 3) | (((b) & 0xf8) >> 3))
-
-#define I915PACKCOLOR8888(r,g,b,a) \
-  ((a<<24) | (r<<16) | (g<<8) | b)
-
-
-
-
-#define BR00_BITBLT_CLIENT   0x40000000
-#define BR00_OP_COLOR_BLT    0x10000000
-#define BR00_OP_SRC_COPY_BLT 0x10C00000
-#define BR13_SOLID_PATTERN   0x80000000
-
-#define XY_COLOR_BLT_CMD		((2<<29)|(0x50<<22)|0x4)
-#define XY_COLOR_BLT_WRITE_ALPHA	(1<<21)
-#define XY_COLOR_BLT_WRITE_RGB		(1<<20)
-
-#define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
-#define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
-#define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
-
-#define XY_SRC_TILED  (1<<15)
-#define XY_DST_TILED  (1<<11)
-
-#define FENCE_LINEAR 0
-#define FENCE_XMAJOR 1
-#define FENCE_YMAJOR 2
-
-#endif