diff options
| author | Ben Widawsky <[email protected]> | 2015-07-14 09:56:09 -0700 |
|---|---|---|
| committer | Ben Widawsky <[email protected]> | 2015-07-16 17:02:35 -0700 |
| commit | 3a31876600cb5c4d90c998ecb5635c602eeb2bd1 (patch) | |
| tree | 0ef7a45ca9ba01f0eae221995e3c8cfd15f1b980 /src/mesa/drivers/dri/i965/intel_tex_image.c | |
| parent | ef42352ff4e1feeea7338db73f540038c6755472 (diff) | |
i965: Push miptree tiling request into flags
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.
The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.
v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)
v3: small fix in assertion requested by Chad
v4: Use parens to get the order right from v3.
Signed-off-by: Ben Widawsky <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_tex_image.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_image.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index e077d5e4743..226aaeb4d54 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -80,8 +80,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw, height, depth, intelImage->base.Base.NumSamples, - INTEL_MIPTREE_TILING_ANY, - layout_flags); + layout_flags | MIPTREE_LAYOUT_ALLOC_ANY_TILED); } static void |