diff options
author | Iago Toral Quiroga <[email protected]> | 2017-01-04 10:46:08 +0100 |
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committer | Iago Toral Quiroga <[email protected]> | 2017-01-05 08:43:46 +0100 |
commit | a98f2e53e1c669dee3114badcce261e564748af4 (patch) | |
tree | 9afbfd07ffa4863f7085247752d5a92389fe9c1a /src/mesa/drivers/dri/i965/intel_screen.c | |
parent | e3123c8ca22e9a9337af6179dfd8383259f3ccc6 (diff) |
i965: add a kernel_features bitfield to intel screen
We can use this to track various features that may or may not be supported
by the hw / kernel. Currently, we usually do this by checking the generation
and supported command parser versions in various places thoughtout the driver
code. With this patch, we centralize all these checks in just once place at
screen creation time, then we just query the bitfield wherever we need to
check if a particular feature is supported.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_screen.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index c3fd6f6685b..c79268f71b3 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1735,7 +1735,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) } if (intel_detect_pipelined_so(screen)) - screen->hw_has_pipelined_register |= HW_HAS_PIPELINED_SOL_OFFSET; + screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES; const char *force_msaa = getenv("INTEL_FORCE_MSAA"); if (force_msaa) { @@ -1773,13 +1773,29 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->cmd_parser_version = 0; } + if (screen->cmd_parser_version >= 2) + screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES; + + /* Haswell requires command parser version 4 in order to have L3 + * atomic scratch1 and chicken3 bits + */ + if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) { + screen->kernel_features |= + KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; + } + /* Haswell requires command parser version 6 in order to write to the * MI_MATH GPR registers, and version 7 in order to use * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). */ - screen->has_mi_math_and_lrr = screen->devinfo.gen >= 8 || - (screen->devinfo.is_haswell && - screen->cmd_parser_version >= 7); + if (screen->devinfo.gen >= 8 || + (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) { + screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; + } + + /* Gen7 needs at least command parser version 5 to support compute */ + if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5) + screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH; dri_screen->extensions = !screen->has_context_reset_notification ? screenExtensions : intelRobustScreenExtensions; |