diff options
| author | Francisco Jerez <[email protected]> | 2014-11-14 20:30:46 +0200 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2015-02-10 19:09:25 +0200 |
| commit | 36a17f0f991323410778392bc2d00f9d911d501b (patch) | |
| tree | 265d7a434fd5a6d6950247af1bd52d113776b936 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c | |
| parent | b40bcd24e0c86fb02c226261c1fe46fb362be217 (diff) | |
i965: Don't tile 1D miptrees.
It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.
v2: Check mt->logical_height0 instead of mt->target (Ken). Add short
comment explaining why they shouldn't be tiled.
Reviewed-by: Neil Roberts <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 64752dd0b86..0e3888f3fbb 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -488,6 +488,13 @@ intel_miptree_choose_tiling(struct brw_context *brw, base_format == GL_DEPTH_STENCIL_EXT) return I915_TILING_Y; + /* 1D textures (and 1D array textures) don't get any benefit from tiling, + * in fact it leads to a less efficient use of memory space and bandwidth + * due to tile alignment. + */ + if (mt->logical_height0 == 1) + return I915_TILING_NONE; + int minimum_pitch = mt->total_width * mt->cpp; /* If the width is much smaller than a tile, don't bother tiling. */ |