i965: Remove CACHED_BATCH support altogether.

Using an unoptimized variant of glamor spending 50% of its CPU time in
brw_draw_prims() (and hitting the cache *very* frequently):

    N           Min           Max        Median           Avg        Stddev
x 200         29200         40500         34900         34750     958.43256
+ 200         31000         40300         34700         34622     916.35941
No difference proven at 95.0% confidence

Similarly, no difference on GLB2.7:

    N           Min           Max        Median           Avg        Stddev
x  63          64.1         71.36         70.69     70.113175     1.6782026
+  63          63.6         71.18         70.75     70.223651     1.6044186
No difference proven at 95.0% confidence

v2: Rebase on master (by anholt)
v3: Add a missing BEGIN_BATCH(3) to aa_line_parameters -- CACHED_BATCH
    didn't have the asserts about batchbuffer usage that ADVANCE_BATCH
    does, so we started assertion failing.

Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

1 files changed, 0 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 80cd571fe13..652a45b5146 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -163,8 +163,6 @@ intel_batchbuffer_advance(struct brw_context *brw)
 #endif
 }
 
-void intel_batchbuffer_cached_advance(struct brw_context *brw);
-
 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING)
 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING)
 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
@@ -175,7 +173,6 @@ void intel_batchbuffer_cached_advance(struct brw_context *brw);
 } while (0)
 
 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
-#define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
 
 #ifdef __cplusplus
 }