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authorEric Anholt <[email protected]>2013-10-02 14:07:40 -0700
committerEric Anholt <[email protected]>2013-10-15 10:18:42 -0700
commit3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 (patch)
tree0b254db5106e9a93aad131d79c6e1399a6301db6 /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
parent5463b5bbbdf133986ac89fd6afdf2bc9622e3ca6 (diff)
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information.
It would be nice to be able to pack our binding table so that programs that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1 binding table entries. To do that, we need the compiled program to have information on where its surfaces go. v2: Rename size to size_bytes to be more explicit. Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_surface_state.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 564ac761658..4488d48e59b 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -451,9 +451,11 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
- &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
+ &brw->wm.base.surf_offset[surf_index]);
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
@@ -495,7 +497,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
GLenum gl_target = rb->TexImage ?
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
- uint32_t surf_index = SURF_INDEX_DRAW(unit);
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
&brw->wm.base.surf_offset[surf_index]);