diff options
| author | Paul Berry <[email protected]> | 2013-08-18 21:18:19 -0700 |
|---|---|---|
| committer | Paul Berry <[email protected]> | 2013-09-11 11:17:14 -0700 |
| commit | 247f90c77e8f3894e963d796628246ba0bde27b5 (patch) | |
| tree | b1711d6cad87d656296970a9c3e828ddb5379d23 /src/mesa/drivers/dri/i965/gen7_gs_state.c | |
| parent | 1a33e0233ad5bfd0b7f62ae25811532c5784653f (diff) | |
i965/gs: Set control data header size/format appropriately for EndPrimitive().
The gen7 geometry shader uses a "control data header" at the beginning
of the output URB entry to store either
(a) flag bits (1 bit/vertex) indicating whether EndPrimitive() was
called after each vertex, or
(b) stream ID bits (2 bits/vertex) indicating which stream each vertex
should be sent to (when multiple transform feedback streams are in
use).
Fortunately, OpenGL only requires separate streams to be supported
when the output type is points, and EndPrimitive() only has an effect
when the output type is line_strip or triangle_strip, so it's not a
problem that these two uses of the control data header are mutually
exclusive.
This patch modifies do_vec4_gs_prog() to determine the correct
hardware settings for configuring the control data header, and
modifies upload_gs_state() to propagate these settings to the
hardware.
In addition, it modifies do_vec4_gs_prog() to ensure that the output
URB entry is large enough to contain both the output vertices *and*
the control data header.
Finally, it modifies vec4_gs_visitor so that it accounts for the size
of the control data header when computing the offset within the URB
where output vertex data should be stored.
Reviewed-by: Ian Romanick <[email protected]>
v2: Fixed incorrect handling of IVB/HSW differences.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_gs_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_gs_state.c | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c index 3e3c33123a4..231e3c98910 100644 --- a/src/mesa/drivers/dri/i965/gen7_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c @@ -95,21 +95,34 @@ upload_gs_state(struct brw_context *brw) OUT_BATCH(0); } - OUT_BATCH(((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) << - GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) | - (brw->gs.prog_data->output_topology << - GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) | - (prog_data->urb_read_length << - GEN6_GS_URB_READ_LENGTH_SHIFT) | - (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) | - (prog_data->dispatch_grf_start_reg << - GEN6_GS_DISPATCH_START_GRF_SHIFT)); - - OUT_BATCH(((brw->max_gs_threads - 1) << max_threads_shift) | - GEN7_GS_DISPATCH_MODE_DUAL_OBJECT | - GEN6_GS_STATISTICS_ENABLE | - GEN7_GS_ENABLE); + uint32_t dw5 = + ((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) << + GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) | + (brw->gs.prog_data->output_topology << + GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) | + (prog_data->urb_read_length << + GEN6_GS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) | + (prog_data->dispatch_grf_start_reg << + GEN6_GS_DISPATCH_START_GRF_SHIFT); + uint32_t dw6 = + ((brw->max_gs_threads - 1) << max_threads_shift) | + (brw->gs.prog_data->control_data_header_size_hwords << + GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) | + GEN7_GS_DISPATCH_MODE_DUAL_OBJECT | + GEN6_GS_STATISTICS_ENABLE | + GEN7_GS_ENABLE; + + if (brw->is_haswell) { + dw6 |= brw->gs.prog_data->control_data_format << + HSW_GS_CONTROL_DATA_FORMAT_SHIFT; + } else { + dw5 |= brw->gs.prog_data->control_data_format << + IVB_GS_CONTROL_DATA_FORMAT_SHIFT; + } + OUT_BATCH(dw5); + OUT_BATCH(dw6); OUT_BATCH(0); ADVANCE_BATCH(); } else { |