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authorTopi Pohjolainen <[email protected]>2015-02-27 11:45:34 +0200
committerTopi Pohjolainen <[email protected]>2015-04-30 00:28:48 +0300
commit7fb0db4dd18e49d3ccdb872f7ed174740301f3a2 (patch)
tree56574132aaebbe74ab24c1c4cdd4450ba8faf633 /src/mesa/drivers/dri/i965/gen7_blorp.cpp
parent25ce6c6943576e22d8d00049578d0e6cc5feea07 (diff)
i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity. On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET) has no effect for native blorp as blorp doesn't use any additional attributes. In fact, regular pipeline setup always uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional attributes. Hence the change makes the two (blorp and regular) consistent. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_blorp.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 12f515d3c83..3065a4c2f46 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
{
BEGIN_BATCH(14);
OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
- OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+ params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
- 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+ BRW_SF_URB_ENTRY_READ_OFFSET <<
+ GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
for (int i = 0; i < 12; ++i)
OUT_BATCH(0);
ADVANCE_BATCH();