i965: Rename the original binding table to mention that it's the WM now.

Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 14 insertions, 14 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a975b2d1c55..a3de2e32da0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -651,7 +651,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  6 * 4, 32, &brw->bind.surf_offset[surf_index]);
+			  6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 
    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 	      BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
@@ -679,7 +679,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   brw->bind.surf_offset[surf_index] + 4,
+			   brw->wm.surf_offset[surf_index] + 4,
 			   intelObj->mt->region->bo, 0,
 			   I915_GEM_DOMAIN_SAMPLER, 0);
 }
@@ -843,7 +843,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
       if (brw->wm.const_bo) {
 	 drm_intel_bo_unreference(brw->wm.const_bo);
 	 brw->wm.const_bo = NULL;
-	 brw->bind.surf_offset[surf_index] = 0;
+	 brw->wm.surf_offset[surf_index] = 0;
 	 brw->state.dirty.brw |= BRW_NEW_SURFACES;
       }
       return;
@@ -864,7 +864,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
 
    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 				       params->NumParameters,
-				       &brw->bind.surf_offset[surf_index]);
+				       &brw->wm.surf_offset[surf_index]);
 
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 }
@@ -885,7 +885,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
    uint32_t *surf;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  6 * 4, 32, &brw->bind.surf_offset[unit]);
+			  6 * 4, 32, &brw->wm.surf_offset[unit]);
 
    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 	      BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
@@ -959,7 +959,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    region = irb->mt->region;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  6 * 4, 32, &brw->bind.surf_offset[unit]);
+			  6 * 4, 32, &brw->wm.surf_offset[unit]);
 
    switch (rb_format) {
    case MESA_FORMAT_SARGB8:
@@ -1027,7 +1027,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    }
 
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   brw->bind.surf_offset[unit] + 4,
+			   brw->wm.surf_offset[unit] + 4,
 			   region->bo,
 			   surf[1] - region->bo->offset,
 			   I915_GEM_DOMAIN_RENDER,
@@ -1095,12 +1095,12 @@ brw_update_texture_surfaces(struct brw_context *brw)
       if (texUnit->_ReallyEnabled) {
 	 brw->intel.vtbl.update_texture_surface(ctx, i);
       } else {
-         brw->bind.surf_offset[surf] = 0;
+         brw->wm.surf_offset[surf] = 0;
       }
 
       /* For now, just mirror the texture setup to the VS slots. */
       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
-	 brw->bind.surf_offset[surf];
+	 brw->wm.surf_offset[surf];
    }
 
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
@@ -1120,7 +1120,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
  * numbers to surface state objects.
  */
 static void
-brw_upload_binding_table(struct brw_context *brw)
+brw_upload_wm_binding_table(struct brw_context *brw)
 {
    uint32_t *bind;
    int i;
@@ -1130,24 +1130,24 @@ brw_upload_binding_table(struct brw_context *brw)
     */
    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 			  sizeof(uint32_t) * BRW_MAX_SURFACES,
-			  32, &brw->bind.bo_offset);
+			  32, &brw->wm.bind_bo_offset);
 
    /* BRW_NEW_SURFACES */
    for (i = 0; i < BRW_MAX_SURFACES; i++) {
-      bind[i] = brw->bind.surf_offset[i];
+      bind[i] = brw->wm.surf_offset[i];
    }
 
    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 }
 
-const struct brw_tracked_state brw_binding_table = {
+const struct brw_tracked_state brw_wm_binding_table = {
    .dirty = {
       .mesa = 0,
       .brw = (BRW_NEW_BATCH |
 	      BRW_NEW_SURFACES),
       .cache = 0
    },
-   .emit = brw_upload_binding_table,
+   .emit = brw_upload_wm_binding_table,
 };
 
 void