diff options
| author | Kenneth Graunke <[email protected]> | 2017-05-07 22:50:20 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-05-10 11:41:58 -0700 |
| commit | 0f34b674ed597dcaf9e6e3af8c074b9cd62bde06 (patch) | |
| tree | 2857deb3541fbbbd83155cde5f6d034459d9d9bc /src/mesa/drivers/dri/i965/brw_wm_state.c | |
| parent | 608a65ebca27668ad060c0735e9209c3fef12d31 (diff) | |
i965: Switch BRW_NEW_CURBE_OFFSETS to BRW_NEW_PUSH_CONSTANT_ALLOCATION.
The BRW_NEW_CURBE_OFFSETS dirty bit is signalled when changing the
partitioning of the Constant Buffer URB section between the various
shader stages, on Gen4-5.
BRW_NEW_PUSH_CONSTANT_ALLOCATION is basically the same thing on Gen7+.
So, save a bit, and use the new name.
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index f018fddbe83..69bbeb26d44 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -148,7 +148,7 @@ brw_upload_wm_unit(struct brw_context *brw) wm->thread3.urb_entry_read_offset = 0; wm->thread3.const_urb_entry_read_length = prog_data->base.curb_read_length; - /* BRW_NEW_CURBE_OFFSETS */ + /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2; if (brw->gen == 5) @@ -263,7 +263,7 @@ const struct brw_tracked_state brw_wm_unit = { _NEW_POLYGONSTIPPLE, .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | - BRW_NEW_CURBE_OFFSETS | + BRW_NEW_PUSH_CONSTANT_ALLOCATION | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | BRW_NEW_PROGRAM_CACHE | |