diff options
| author | Matt Turner <[email protected]> | 2014-06-28 13:53:55 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2014-06-30 22:31:05 -0700 |
| commit | 35b741c8e74cf7c6a99d513c1fd01477545a172d (patch) | |
| tree | fbf63bef50abcb0f3339d2965c421104e2b87c41 /src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | |
| parent | d35f34cea9558c23700532d4a7142dab2cc342a8 (diff) | |
i965/vec4: Pass const references to instruction functions.
text data bss dec hex filename
4231165 123200 39648 4394013 430c1d i965_dri.so
4186277 123200 39648 4349125 425cc5 i965_dri.so
Cuts 43k of .text and saves a bunch of useless struct copies.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index c732c90068c..219515a9c2a 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -112,7 +112,7 @@ vec4_visitor::emit(enum opcode opcode) #define ALU1(op) \ vec4_instruction * \ - vec4_visitor::op(dst_reg dst, src_reg src0) \ + vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \ { \ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \ src0); \ @@ -120,7 +120,8 @@ vec4_visitor::emit(enum opcode opcode) #define ALU2(op) \ vec4_instruction * \ - vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \ + vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \ + const src_reg &src1) \ { \ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \ src0, src1); \ @@ -128,7 +129,8 @@ vec4_visitor::emit(enum opcode opcode) #define ALU2_ACC(op) \ vec4_instruction * \ - vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \ + vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \ + const src_reg &src1) \ { \ vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, \ BRW_OPCODE_##op, dst, src0, src1); \ @@ -138,7 +140,8 @@ vec4_visitor::emit(enum opcode opcode) #define ALU3(op) \ vec4_instruction * \ - vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\ + vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \ + const src_reg &src1, const src_reg &src2) \ { \ assert(brw->gen >= 6); \ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \ @@ -238,7 +241,7 @@ vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition) } vec4_instruction * -vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index) +vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index) { vec4_instruction *inst; @@ -251,7 +254,8 @@ vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index) } vec4_instruction * -vec4_visitor::SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index) +vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src, + const src_reg &index) { vec4_instruction *inst; |