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author | Neil Roberts <[email protected]> | 2015-02-20 19:11:46 +0000 |
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committer | Neil Roberts <[email protected]> | 2015-04-20 22:03:21 -0700 |
commit | 584f8e1ec56b45057b53e161233308f38e1c3b09 (patch) | |
tree | bc5f67152f1a846d6e5f790b599e897ae4da48e8 /src/mesa/drivers/dri/i965/brw_tex_layout.c | |
parent | c1485f4b7d044724b3dbc1011f3c3a8a53132010 (diff) |
i965/skl: Don't use ALL_SLICES_AT_EACH_LOD
The render surface state command for Skylake doesn't have the surface
array spacing bit so it's not possible to select this layout. I think
it was only used in order to make it pick a tightly-packed qpitch
value that doesn't include space for the mipmaps. However this won't
be necessary after the next patch because it will automatically pick a
packed qpitch value whenever first_level==last_level. It is better to
remove this layout entirely on Gen8+ because although it can
effectively be implemented with a small qpitch value when there are no
mipmaps it isn't possible to support the case where there are mipmaps
because in that case the layout is very different.
It could be good to make a similar change for Gen8 if we also change
the layouting code to pick the qpitch value in a similar way.
v2: Make the commit message and comments more convincing
Reviewed-by: Ben Widawsky <[email protected]>
Tested-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_tex_layout.c')
0 files changed, 0 insertions, 0 deletions