i965: Micro-optimize swizzle_to_scs() and make it inlinable.

brw_swizzle_to_scs has been showing up in my CPU profiling, which is
rather silly - it's a tiny amount of code.  It really should be inlined,
and can easily be implemented with fewer instructions.

The enum translation is as follows:

SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
        0          1          2          3             4            5
        4          5          6          7             0            1
  SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE

which is simply (swizzle + 4) & 7.

Haswell needs extra textureGather workarounds to remap GREEN to BLUE,
but Broadwell and later do not.

This patch replicates swizzle_to_scs in gen7_wm_surface_state.c and
gen8_surface_state.c, since the Gen8+ code can be simplified to a mere
two instructions.  Both copies can be marked static for easy inlining.

v2: Put the commit message in the code as comments (requested by
    Jason Ekstrand).  Also fix a typo.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>

1 files changed, 0 insertions, 1 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 399347c15fe..f195407e882 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -225,7 +225,6 @@ int brw_get_texture_swizzle(const struct gl_context *ctx,
                             const struct gl_texture_object *t);
 
 /* gen7_wm_surface_state.c */
-unsigned brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue);
 uint32_t gen7_surface_tiling_mode(uint32_t tiling);
 uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout l);
 void gen7_set_surface_mcs_info(struct brw_context *brw,