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authorJordan Justen <[email protected]>2017-02-25 02:30:06 -0800
committerJordan Justen <[email protected]>2017-10-31 23:46:53 -0700
commit1a61a8b9a7c7cdbb42b74a76c2ec825f7107cc83 (patch)
tree5527eaff0dbb79bae3f4b5bc60f314be6d04728a /src/mesa/drivers/dri/i965/brw_state.h
parentccb700526f647e0d02cb1c500b6aee083ba1b9d7 (diff)
i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false
(Apologies for the double negative.) For now, the shader cache is disabled by default on i965 to allow us to verify its stability. In other words, to enable the shader cache on i965, set MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then the shader cache will be disabled. We use the build-id of i965_dri.so for the timestamp, and the pci device id for the device name. v2: * Simplify code by forcing link to include build id sha. (Matt) v3: * Don't use a for loop with snprintf for bin to hex. (Matt) * Assume fixed length render and timestamp string to further simplify code. Cc: Matt Turner <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index c98b7facd57..927e77920ef 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,6 +132,7 @@ void gen8_write_pma_stall_bits(struct brw_context *brw,
uint32_t pma_stall_bits);
/* brw_disk_cache.c */
+void brw_disk_cache_init(struct brw_context *brw);
bool brw_disk_cache_upload_program(struct brw_context *brw,
gl_shader_stage stage);
void brw_disk_cache_write_compute_program(struct brw_context *brw);