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authorKenneth Graunke <[email protected]>2013-11-04 23:19:55 -0800
committerKenneth Graunke <[email protected]>2014-01-31 17:50:08 -0800
commit4c4e0ed64bceca57e19c0a9f53aae77d795aa937 (patch)
tree50c6927258e4983f99ee5457ad4d4b27c79a2dc7 /src/mesa/drivers/dri/i965/brw_primitive_restart.c
parenta0d4311072267aa5427eb2cacd820e96f114eba0 (diff)
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes: - 48-bit relocations - Thread count is specified as U/2-1 instead of U-1. - An extra DWord (DW9) with clip planes, URB entry output length/offsets - We need to program the "Expected Vertex Count" (VerticesIn) v2: Set the number of binding table entries so they can be prefetched (requested by Eric Anholt). v3: Add a WARN_ONCE for a missing workaround. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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