diff options
author | Kenneth Graunke <[email protected]> | 2017-11-16 23:43:48 -0800 |
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committer | Kenneth Graunke <[email protected]> | 2018-03-27 18:41:44 -0700 |
commit | 2c01215c1b2c80817cbc6bcdbecd3f19029b287d (patch) | |
tree | ca2b2455d9ad41993e6a21a4e26a0f1cd152a7ea /src/mesa/drivers/dri/i965/brw_misc_state.c | |
parent | 5f21a7afe072f8a6e558ccc47407a0a94e0d1313 (diff) |
i965: Drop PIPE_CONTROL_NO_WRITE from various calls.
This is just zero - passing nothing already gives us a post-sync
operation of "nothing".
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 29d74876c27..05517ebf587 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -462,15 +462,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | dc_flush | - PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_STATE_CACHE_INVALIDATE | - PIPE_CONTROL_INSTRUCTION_INVALIDATE | - PIPE_CONTROL_NO_WRITE); + PIPE_CONTROL_INSTRUCTION_INVALIDATE); } else { /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] |