diff options
| author | Kenneth Graunke <[email protected]> | 2017-01-24 00:45:53 -0800 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2017-02-03 11:08:55 +0000 |
| commit | 31715781c62f506875a7fea017aff64fdac643af (patch) | |
| tree | 2fe99d596fd1b3ada98c7dfde93dc189c2c9b32b /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
| parent | ebfe5e17ee5e484737dd7055df0f6542983473ac (diff) | |
i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.
SIMD16 compute shaders use a send(16) with mlen 1 for the EOT message,
using a source of g127 for the single register. With a UD type, this
supposedly could read g128, which doesn't exist, causing the simulator
to get cranky. Use a UW type to avoid this.
Cc: "17.0" <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
(cherry picked from commit fcf723b647f36fa174d29b1fe6a9732637a1f8d1)
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 0710be932a5..26ffbb169d2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -508,7 +508,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload) insn = brw_next_insn(p, BRW_OPCODE_SEND); brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); - brw_set_src0(p, insn, payload); + brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW)); brw_set_src1(p, insn, brw_imm_d(0)); /* Terminate a compute shader by sending a message to the thread spawner. |