diff options
| author | Chris Forbes <[email protected]> | 2013-01-24 21:35:15 +1300 |
|---|---|---|
| committer | Chris Forbes <[email protected]> | 2013-03-02 11:40:49 +1300 |
| commit | f52ce6a0ca73d1cd89091689efd8ea2e14748723 (patch) | |
| tree | 5e6037eae92c8fcb30857db1f30c8a9d11501a7c /src/mesa/drivers/dri/i965/brw_fs_emit.cpp | |
| parent | 555dc6d74de76becac30289c6da0205489057a21 (diff) | |
i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS
This is very similar to the TXF opcode, but lowers to `ld2dms` rather
than `ld` on Gen7.
V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks
it actually writes the correct number of registers. Otherwise in
nontrivial shaders some of the registers tend to get clobbered,
producing bad results.
Signed-off-by: Chris Forbes <[email protected]>
Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_emit.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index a25f594d9d8..2391ad12026 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -398,6 +398,12 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src case SHADER_OPCODE_TXF: msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; break; + case SHADER_OPCODE_TXF_MS: + if (intel->gen >= 7) + msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS; + else + msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; + break; default: assert(!"not reached"); break; @@ -1236,6 +1242,7 @@ fs_generator::generate_code(exec_list *instructions) case FS_OPCODE_TXB: case SHADER_OPCODE_TXD: case SHADER_OPCODE_TXF: + case SHADER_OPCODE_TXF_MS: case SHADER_OPCODE_TXL: case SHADER_OPCODE_TXS: generate_tex(inst, dst, src[0]); |