i965: Replace guess_execution_size with something simpler.

guess_execution_size() does two things:

   1. Cope with small destination registers.
   2. Cope with SIMD8 vs SIMD16 mode.

This patch replaces the first with a simple if block in brw_set_dest: if
the destination register width is less than 8, you probably want the
execution size to match.  (I didn't put this in the 3src block because
it doesn't seem to matter.)

Since only the FS compiler cares about SIMD16 mode, it's easy to just
set the default execution size there.

This pattern was already been proven in the Gen8+ generator, but we
didn't port it back to the existing generator when we combined the two.

This is based on a patch from Ken from about a year ago. I've rebased it
and and fixed a few bugs.

Reviewed-by: Jason Ekstrand <[email protected]>

1 files changed, 9 insertions, 23 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 1fe9e7bc73d..706b66bc548 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -36,25 +36,6 @@
 
 #include "util/ralloc.h"
 
-/***********************************************************************
- * Internal helper for constructing instructions
- */
-
-static void guess_execution_size(struct brw_compile *p,
-				 brw_inst *insn,
-				 struct brw_reg reg)
-{
-   const struct brw_context *brw = p->brw;
-
-   if (reg.width == BRW_WIDTH_8 && p->compressed) {
-      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
-   } else {
-      /* Register width definitions are compatible with BRW_EXECUTE_* enums. */
-      brw_inst_set_exec_size(brw, insn, reg.width);
-   }
-}
-
-
 /**
  * Prior to Sandybridge, the SEND instruction accepted non-MRF source
  * registers, implicitly moving the operand to a message register.
@@ -76,6 +57,7 @@ gen6_resolve_implied_move(struct brw_compile *p,
 
    if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) {
       brw_push_insn_state(p);
+      brw_set_default_exec_size(p, BRW_EXECUTE_8);
       brw_set_default_mask_control(p, BRW_MASK_DISABLE);
       brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
       brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
@@ -215,10 +197,12 @@ brw_set_dest(struct brw_compile *p, brw_inst *inst, struct brw_reg dest)
       }
    }
 
-   /* NEW: Set the execution size based on dest.width and
-    * inst->compression_control:
+   /* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
+    * or 16 (SIMD16), as that's normally correct.  However, when dealing with
+    * small registers, we automatically reduce it to match the register size.
     */
-   guess_execution_size(p, inst, dest);
+   if (dest.width < BRW_EXECUTE_8)
+      brw_inst_set_exec_size(brw, inst, dest.width);
 }
 
 extern int reg_type_size[];
@@ -874,7 +858,6 @@ brw_alu3(struct brw_compile *p, unsigned opcode, struct brw_reg dest,
    brw_inst_set_3src_dst_reg_nr(brw, inst, dest.nr);
    brw_inst_set_3src_dst_subreg_nr(brw, inst, dest.subnr / 16);
    brw_inst_set_3src_dst_writemask(brw, inst, dest.dw1.bits.writemask);
-   guess_execution_size(p, inst, dest);
 
    assert(src0.file == BRW_GENERAL_REGISTER_FILE);
    assert(src0.address_mode == BRW_ADDRESS_DIRECT);
@@ -2015,6 +1998,7 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
     */
    {
       brw_push_insn_state(p);
+      brw_set_default_exec_size(p, BRW_EXECUTE_8);
       brw_set_default_mask_control(p, BRW_MASK_DISABLE);
       brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 
@@ -2135,6 +2119,7 @@ brw_oword_block_read_scratch(struct brw_compile *p,
 
    {
       brw_push_insn_state(p);
+      brw_set_default_exec_size(p, BRW_EXECUTE_8);
       brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
       brw_set_default_mask_control(p, BRW_MASK_DISABLE);
 
@@ -2228,6 +2213,7 @@ void brw_oword_block_read(struct brw_compile *p,
    mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
 
    brw_push_insn_state(p);
+   brw_set_default_exec_size(p, BRW_EXECUTE_8);
    brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);