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authorChris Wilson <[email protected]>2017-01-10 21:23:26 +0000
committerKenneth Graunke <[email protected]>2017-03-02 00:30:41 -0800
commit92281b2c7f61d6fb8f7cc43eac15bb487f1e9848 (patch)
treed55135b8de48b3a374ad575b11d5d51f65d65772 /src/mesa/drivers/dri/i965/brw_draw_upload.c
parent7ad692d8e2bf619f5855552e3d56aafa9f5f21af (diff)
i965: Only flush the batchbuffer if we need to zero the SO offsets
If we don't have pipelined register access (e.g. Haswell before kernel v4.2), then we can only implement EXT_transform_feedback by reseting the SO offsets *between* batches. However, if we do have pipelined access to the SO registers on gen7, we can simply emit an inline reset of the SO registers without a full batch flush. v2 [by Ken]: Simplify after recent kernel feature detection changes. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw_upload.c')
0 files changed, 0 insertions, 0 deletions