diff options
| author | Kristian Høgsberg <[email protected]> | 2014-10-20 23:05:09 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2014-12-10 12:29:04 -0800 |
| commit | c5b3878714a75dab40439622050b2ce6f60337c0 (patch) | |
| tree | 869545b0693e5ed463edb206c54cd3f8935f2e31 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f (diff) | |
i965: Add new SIMD8 VS prog data flag
This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 843ef32cbbd..28e398d0b88 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1697,6 +1697,8 @@ enum brw_message_target { # define GEN6_VS_STATISTICS_ENABLE (1 << 10) # define GEN6_VS_CACHE_DISABLE (1 << 1) # define GEN6_VS_ENABLE (1 << 0) +/* Gen8+ DW7 */ +# define GEN8_VS_SIMD8_ENABLE (1 << 2) /* Gen8+ DW8 */ # define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21 # define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16 |