diff options
| author | Jordan Justen <[email protected]> | 2015-06-11 19:17:03 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2015-07-14 14:44:48 -0700 |
| commit | 320089dbd63de3ac1bd3d42ee8cec41837486d8c (patch) | |
| tree | c283e313a874a402190388e1a33cf5ad76331a26 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | cd7dd45bfec9ad68719c5e4e04b66ea4bcc1a2c1 (diff) | |
i965/cs: Initialize GPGPU Thread Count
This field should always be set for gen8. In the bdw PRM, Volume 2d:
Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD
6, Bits 9:0, Number of Threads in GPGPU Thread Group:
"This field should not be set to 0 even if the barrier is disabled,
since an accurate value is needed for proper pre-emption."
In the HSW PRM, the it doesn't mention that it must always be set, but
it should not hurt.
Reported-by: Kristian Høgsberg <[email protected]>
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 19489aba5be..b1a1c11b3ae 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2518,6 +2518,11 @@ enum brw_wm_barycentric_interp_mode { # define MEDIA_VFE_STATE_CURBE_ALLOC_MASK INTEL_MASK(15, 0) #define MEDIA_INTERFACE_DESCRIPTOR_LOAD 0x7002 +/* GEN7 DW5, GEN8+ DW6 */ +# define MEDIA_GPGPU_THREAD_COUNT_SHIFT 0 +# define MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(7, 0) +# define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT 0 +# define GEN8_MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(9, 0) #define MEDIA_STATE_FLUSH 0x7004 #define GPGPU_WALKER 0x7105 /* GEN8+ DW2 */ |